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2026-07-09 22:48:08 +02:00
parent 50dbc682d9
commit 49c9e6315b
56 changed files with 309162 additions and 2007410 deletions

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RTL/RgmiiReset.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module RgmiiReset(
input clock,
reset,
output io_ethernet_reset,
input io_pll_locked
);
reg [1:0] state;
reg timer;
wire _GEN = state == 2'h0;
wire _GEN_0 = state == 2'h1;
always @(posedge clock) begin
if (reset) begin
state <= 2'h0;
timer <= 1'h0;
end
else begin
if (_GEN)
state <= {1'h0, io_pll_locked};
timer <= ~_GEN & (_GEN_0 ? timer - 1'h1 : state == 2'h2 ? timer - 1'h1 : timer);
end
end // always @(posedge)
assign io_ethernet_reset = _GEN | _GEN_0 | state != 2'h2;
endmodule