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gogogaga

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This commit is contained in:
Albin Chaboissier
2026-07-09 22:48:08 +02:00
parent 50dbc682d9
commit 49c9e6315b
56 changed files with 309162 additions and 2007410 deletions
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RTL/Top.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module Top(
input clk,
irst,
output [3:0] leds,
output txp,
RGMII_GTXCLK,
PHY_CLK,
input RGMII_RXCK,
RGMII_RXD_0,
RGMII_RXD_1,
RGMII_RXD_2,
RGMII_RXD_3,
RGMII_RXDV,
output RGMII_RST_N,
RGMII_TXEN
);
wire _uart_tx_io_data_ready;
wire _uart_ce_io_output_ce;
wire _iddr_dv_io_output_data_0;
wire [3:0] _iddr_io_output_data_0;
wire [3:0] _iddr_io_output_data_1;
wire _byte_queue_read_io_deq_valid;
wire [7:0] _byte_queue_read_io_deq_bits;
wire _ethernet_clock_lock;
wire _rgmii_rxdv_dly2_DO;
wire _rgmii_rxdv_dly_DO;
wire _rgmii_rxd_dly2_3_DO;
wire _rgmii_rxd_dly1_3_DO;
wire _rgmii_rxd_dly2_2_DO;
wire _rgmii_rxd_dly1_2_DO;
wire _rgmii_rxd_dly2_1_DO;
wire _rgmii_rxd_dly1_1_DO;
wire _rgmii_rxd_dly2_DO;
wire _rgmii_rxd_dly1_DO;
wire [7:0] normal_byte = {_iddr_io_output_data_1, _iddr_io_output_data_0};
reg [3:0] skewed_byte_REG;
wire [7:0] skewed_byte = {_iddr_io_output_data_0, skewed_byte_REG};
reg normal_preamble_seen;
reg skewed_preamble_seen;
reg [1:0] ethernet_state;
wire _GEN = ethernet_state == 2'h0;
wire [3:0][7:0] _GEN_0 = {{8'h0}, {skewed_byte}, {normal_byte}, {8'h0}};
always @(posedge RGMII_RXCK) begin
skewed_byte_REG <= _iddr_io_output_data_1;
if (~irst) begin
normal_preamble_seen <= 1'h0;
skewed_preamble_seen <= 1'h0;
ethernet_state <= 2'h0;
end
else begin
automatic logic _GEN_1;
automatic logic _GEN_2;
automatic logic _GEN_3;
_GEN_1 = normal_preamble_seen & normal_byte == 8'hD5;
_GEN_2 = _GEN & _iddr_dv_io_output_data_0;
_GEN_3 = skewed_preamble_seen & skewed_byte == 8'hD5;
if (_GEN_2) begin
normal_preamble_seen <= ~_GEN_1 & (normal_byte == 8'h55 | normal_preamble_seen);
skewed_preamble_seen <= ~_GEN_3 & (skewed_byte == 8'h55 | skewed_preamble_seen);
end
if (_iddr_dv_io_output_data_0) begin
if (_GEN_2) begin
if (_GEN_3)
ethernet_state <= 2'h2;
else if (_GEN_1)
ethernet_state <= 2'h1;
end
end
else
ethernet_state <= 2'h0;
end
end // always @(posedge)
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1 (
.DI (RGMII_RXD_0),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly1_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2 (
.DI (_rgmii_rxd_dly1_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly2_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_1 (
.DI (RGMII_RXD_1),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly1_1_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_1 (
.DI (_rgmii_rxd_dly1_1_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly2_1_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_2 (
.DI (RGMII_RXD_2),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly1_2_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_2 (
.DI (_rgmii_rxd_dly1_2_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly2_2_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_3 (
.DI (RGMII_RXD_3),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly1_3_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_3 (
.DI (_rgmii_rxd_dly1_3_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly2_3_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxdv_dly (
.DI (RGMII_RXDV),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxdv_dly_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(200),
.DYN_DLY_EN("FALSE")
) rgmii_rxdv_dly2 (
.DI (_rgmii_rxdv_dly_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxdv_dly2_DO),
.DF (/* unused */)
);
ether_pll ethernet_clock (
.clkin (clk),
.init_clk (clk),
.clkout0 (RGMII_GTXCLK),
.clkout1 (PHY_CLK),
.lock (_ethernet_clock_lock)
);
AysncFifo byte_queue (
.write_io_clk (RGMII_RXCK),
.write_io_enq_valid
(~(~_iddr_dv_io_output_data_0 | _GEN)
& (ethernet_state == 2'h1 | ethernet_state == 2'h2)),
.write_io_enq_bits (_GEN_0[ethernet_state]),
.read_io_clk (clk),
.read_io_deq_ready (_uart_tx_io_data_ready),
.read_io_deq_valid (_byte_queue_read_io_deq_valid),
.read_io_deq_bits (_byte_queue_read_io_deq_bits)
);
NIddr iddr (
.clock (RGMII_RXCK),
.io_input_data
({_rgmii_rxd_dly2_3_DO,
_rgmii_rxd_dly2_2_DO,
_rgmii_rxd_dly2_1_DO,
_rgmii_rxd_dly2_DO}),
.io_output_data_0 (_iddr_io_output_data_0),
.io_output_data_1 (_iddr_io_output_data_1)
);
NIddr_1 iddr_dv (
.clock (RGMII_RXCK),
.io_input_data (_rgmii_rxdv_dly2_DO),
.io_output_data_0 (_iddr_dv_io_output_data_0)
);
RgmiiReset ethernet_reset (
.clock (clk),
.reset (~irst),
.io_ethernet_reset (RGMII_RST_N),
.io_pll_locked (_ethernet_clock_lock)
);
UartClockEnable uart_ce (
.clock (clk),
.reset (~irst),
.io_output_ce (_uart_ce_io_output_ce)
);
UartTx uart_tx (
.clock (clk),
.reset (~irst),
.io_data_ready (_uart_tx_io_data_ready),
.io_data_valid (_byte_queue_read_io_deq_valid),
.io_data_bits (_byte_queue_read_io_deq_bits),
.io_signal (txp),
.io_clock_enable (_uart_ce_io_output_ce)
);
assign leds = 4'h0;
assign RGMII_TXEN = 1'h0;
endmodule