gogogaga

RTL/UartTx.sv

@@ -0,0 +1,61 @@
+// Generated by CIRCT firtool-1.139.0
+module UartTx(
+  input        clock,
+               reset,
+  output       io_data_ready,
+  input        io_data_valid,
+  input  [7:0] io_data_bits,
+  output       io_signal,
+  input        io_clock_enable
+);
+
+  reg  [1:0] state;
+  reg  [7:0] data;
+  reg        data_waiting;
+  reg  [2:0] bit_counter;
+  reg  [7:0] stop_bit_wait;
+  wire       _GEN = state == 2'h0;
+  wire       _GEN_0 = state == 2'h1;
+  wire       _GEN_1 = state == 2'h2;
+  wire [7:0] _io_signal_T = data >> bit_counter;
+  always @(posedge clock) begin
+    automatic logic _GEN_2;
+    _GEN_2 = ~data_waiting & io_data_valid;
+    if (reset) begin
+      state <= 2'h0;
+      data_waiting <= 1'h0;
+      stop_bit_wait <= 8'h0;
+    end
+    else begin
+      automatic logic _GEN_3;
+      automatic logic _GEN_4;
+      automatic logic _GEN_5 = _GEN | _GEN_0 | _GEN_1;
+      _GEN_3 = stop_bit_wait == 8'h14;
+      _GEN_4 = (&state) & _GEN_3;
+      if (io_clock_enable) begin
+        automatic logic [3:0][1:0] _GEN_6;
+        _GEN_6 =
+          {{_GEN_4 ? 2'h0 : state},
+           {{1'h1, &bit_counter}},
+           {2'h2},
+           {{1'h0, data_waiting}}};
+        state <= _GEN_6[state];
+      end
+      data_waiting <= (~io_clock_enable | _GEN_5 | ~_GEN_4) & (_GEN_2 | data_waiting);
+      if (~io_clock_enable | _GEN_5 | ~(&state)) begin
+      end
+      else
+        stop_bit_wait <= _GEN_3 ? 8'h0 : stop_bit_wait + 8'h1;
+    end
+    if (_GEN_2)
+      data <= io_data_bits;
+    if (io_clock_enable) begin
+      automatic logic [3:0][2:0] _GEN_7 =
+        {{bit_counter}, {bit_counter + 3'h1}, {3'h0}, {bit_counter}};
+      bit_counter <= _GEN_7[state];
+    end
+  end // always @(posedge)
+  assign io_data_ready = ~data_waiting;
+  assign io_signal = _GEN | ~_GEN_0 & (~_GEN_1 | _io_signal_T[0]);
+endmodule
+