module RgmiiReset (
	clock,
	reset,
	io_ethernet_reset,
	io_pll_locked
);
	input clock;
	input reset;
	output wire io_ethernet_reset;
	input io_pll_locked;
	reg [1:0] state;
	reg timer;
	wire _GEN = state == 2'h0;
	wire _GEN_0 = state == 2'h1;
	always @(posedge clock)
		if (reset) begin
			state <= 2'h0;
			timer <= 1'h0;
		end
		else begin
			if (_GEN)
				state <= {1'h0, io_pll_locked};
			timer <= ~_GEN & (_GEN_0 ? timer - 1'h1 : (state == 2'h2 ? timer - 1'h1 : timer));
		end
	assign io_ethernet_reset = (_GEN | _GEN_0) | (state != 2'h2);
endmodule