// Generated by CIRCT firtool-1.139.0
module UartClockEnable(
  input  clock,
         reset,
  output io_output_ce
);

  reg  [31:0] counter;
  wire [32:0] sum = {1'h0, counter} + 33'h96FEB5;
  always @(posedge clock) begin
    if (reset)
      counter <= 32'h0;
    else
      counter <= sum[31:0];
  end // always @(posedge)
  assign io_output_ce = sum[32];
endmodule