module UartClockEnable (
	clock,
	reset,
	io_output_ce
);
	input clock;
	input reset;
	output wire io_output_ce;
	reg [31:0] counter;
	wire [32:0] sum = {1'h0, counter} + 33'h00096feb5;
	always @(posedge clock)
		if (reset)
			counter <= 32'h00000000;
		else
			counter <= sum[31:0];
	assign io_output_ce = sum[32];
endmodule