module mem_1024x8 (
	R0_addr,
	R0_en,
	R0_clk,
	R0_data,
	W0_addr,
	W0_en,
	W0_clk,
	W0_data
);
	input [9:0] R0_addr;
	input R0_en;
	input R0_clk;
	output wire [7:0] R0_data;
	input [9:0] W0_addr;
	input W0_en;
	input W0_clk;
	input [7:0] W0_data;
	reg [7:0] Memory [0:1023];
	reg _R0_en_d0;
	reg [9:0] _R0_addr_d0;
	always @(posedge R0_clk) begin
		_R0_en_d0 <= R0_en;
		_R0_addr_d0 <= R0_addr;
	end
	always @(posedge W0_clk)
		if (W0_en)
			Memory[W0_addr] <= W0_data;
	assign R0_data = (_R0_en_d0 ? Memory[_R0_addr_d0] : 8'bxxxxxxxx);
endmodule