// Generated by CIRCT firtool-1.139.0
module RgmiiReset(
  input  clock,
         reset,
  output io_ethernet_reset,
  input  io_pll_locked
);

  reg  [1:0] state;
  reg        timer;
  wire       _GEN = state == 2'h0;
  wire       _GEN_0 = state == 2'h1;
  always @(posedge clock) begin
    if (reset) begin
      state <= 2'h0;
      timer <= 1'h0;
    end
    else begin
      if (_GEN)
        state <= {1'h0, io_pll_locked};
      timer <= ~_GEN & (_GEN_0 ? timer - 1'h1 : state == 2'h2 ? timer - 1'h1 : timer);
    end
  end // always @(posedge)
  assign io_ethernet_reset = _GEN | _GEN_0 | state != 2'h2;
endmodule