module \std::cdc::sync2[1531] ( clk_i, input_i, output__ ); input clk_i; input input_i; output wire output__; wire \clk ; assign \clk = clk_i; wire \input ; assign \input = input_i; (* src = "/stdlib/cdc.spade:14,14" *) reg \sync1 ; (* src = "/stdlib/cdc.spade:15,14" *) reg \sync2 ; always @(posedge \clk ) \sync1 <= \input ; always @(posedge \clk ) \sync2 <= \sync1 ; assign output__ = \sync2 ; endmodule module \std::cdc::sync2_bool ( clk_i, input_i, output__ ); input clk_i; input input_i; output wire output__; wire \clk ; assign \clk = clk_i; wire \input ; assign \input = input_i; (* src = "/stdlib/cdc.spade:31,14" *) wire _e_544; (* src = "/stdlib/cdc.spade:31,14" *) \std::cdc::sync2[1531] \sync2_0 ( .clk_i(\clk ), .input_i(\input ), .output__(_e_544) ); assign output__ = _e_544; endmodule module \std::conv::tri_to_bool ( t_i, output__ ); input t_i; output wire output__; wire \t ; assign \t = t_i; (* src = "/stdlib/conv.spade:80,5" *) wire _e_828; (* src = "/stdlib/conv.spade:80,5" *) \std::conv::impl#12::as_bool \as_bool_0 ( .self_i(\t ), .output__(_e_828) ); assign output__ = _e_828; endmodule module \std::io::rising_edge ( clk_i, value_i, output__ ); input clk_i; input value_i; output wire output__; wire \clk ; assign \clk = clk_i; wire \value ; assign \value = value_i; (* src = "/stdlib/io.spade:12,14" *) reg \old_value ; (* src = "/core/ops.spade:255,29" *) wire _e_2202; (* src = "/core/ops.spade:255,9" *) wire _e_2201; (* src = "/core/ops.spade:255,9" *) wire _e_1034; (* src = "/core/ops.spade:297,29" *) wire _e_2210; (* src = "/core/ops.spade:297,37" *) wire _e_2211; (* src = "/core/ops.spade:297,9" *) wire _e_2209; (* src = "/core/ops.spade:297,9" *) wire _e_1032; always @(posedge \clk ) \old_value <= \value ; assign _e_2202 = {\old_value }; assign _e_2201 = ~_e_2202; assign _e_1034 = _e_2201; assign _e_2210 = {\value }; assign _e_2211 = {_e_1034}; assign _e_2209 = _e_2210 & _e_2211; assign _e_1032 = _e_2209; assign output__ = _e_1032; endmodule module \std::io::falling_edge ( clk_i, value_i, output__ ); input clk_i; input value_i; output wire output__; wire \clk ; assign \clk = clk_i; wire \value ; assign \value = value_i; (* src = "/stdlib/io.spade:27,14" *) reg \old_value ; (* src = "/core/ops.spade:255,29" *) wire _e_2220; (* src = "/core/ops.spade:255,9" *) wire _e_2219; (* src = "/core/ops.spade:255,9" *) wire _e_2218; (* src = "/core/ops.spade:297,29" *) wire _e_2228; (* src = "/core/ops.spade:297,37" *) wire _e_2229; (* src = "/core/ops.spade:297,9" *) wire _e_2227; (* src = "/core/ops.spade:297,9" *) wire _e_2226; always @(posedge \clk ) \old_value <= \value ; assign _e_2220 = {\value }; assign _e_2219 = ~_e_2220; assign _e_2218 = _e_2219; assign _e_2228 = {_e_2218}; assign _e_2229 = {\old_value }; assign _e_2227 = _e_2228 & _e_2229; assign _e_2226 = _e_2227; assign output__ = _e_2226; endmodule module main ( clk, leds, tmds_clk, tmds ); input clk; output wire [3:0] leds; output wire tmds_clk; output wire [2:0] tmds; wire [3:0] \leds_mut ; assign leds = \leds_mut ; wire \tmds_clk_mut ; assign tmds_clk = \tmds_clk_mut ; wire [2:0] \tmds_mut ; assign tmds = \tmds_mut ; (* src = "src/main.spade:9,35" *) wire _e_2156; (* src = "src/main.spade:9,35" *) wire _e_2157_mut; (* src = "src/main.spade:9,35" *) wire _e_1733; (* src = "src/main.spade:9,35" *) wire _e_1733_mut; (* src = "src/main.spade:9,9" *) wire \clk_pll ; (* src = "src/main.spade:9,9" *) wire \clk_pll_wire_mut ; (* src = "src/main.spade:10,37" *) wire _e_2158; (* src = "src/main.spade:10,37" *) wire _e_2159_mut; (* src = "src/main.spade:10,37" *) wire _e_1737; (* src = "src/main.spade:10,37" *) wire _e_1737_mut; (* src = "src/main.spade:10,9" *) wire \lock_pll ; (* src = "src/main.spade:10,9" *) wire \lock_pll_wire_mut ; localparam [31:0] _e_1748 = 32'd50000000; (* src = "/core/ops.spade:53,9" *) wire _e_1746; localparam [31:0] _e_1750 = 32'd0; localparam [31:0] _e_1754 = 32'd1; (* src = "src/main.spade:13,75" *) wire [31:0] _e_1752; (* src = "src/main.spade:13,38" *) wire [31:0] _e_1745; (* src = "src/main.spade:13,18" *) reg [31:0] \counter ; localparam [31:0] _e_1760 = 32'd0; (* src = "/core/ops.spade:53,9" *) wire _e_1758; (* src = "/core/ops.spade:255,29" *) wire _e_2242; (* src = "/core/ops.spade:255,9" *) wire _e_2241; (* src = "/core/ops.spade:255,9" *) wire _e_1762; (* src = "src/main.spade:14,29" *) wire _e_1757; (* src = "src/main.spade:14,18" *) reg \on ; localparam [0:0] _e_1770 = 0; localparam [0:0] _e_1771 = 0; localparam [0:0] _e_1772 = 0; (* src = "src/main.spade:19,16" *) wire [2:0] _e_1769; (* src = "/core/ops.spade:255,29" *) wire _e_2250; (* src = "/core/ops.spade:255,9" *) wire _e_2249; (* src = "/core/ops.spade:255,9" *) wire _e_2248; (* src = "/core/ops.spade:255,29" *) wire _e_2258; (* src = "/core/ops.spade:255,9" *) wire _e_2257; (* src = "/core/ops.spade:255,9" *) wire _e_1777; (* src = "/core/ops.spade:255,29" *) wire _e_2266; (* src = "/core/ops.spade:255,9" *) wire _e_2265; (* src = "/core/ops.spade:255,9" *) wire _e_2264; (* src = "/core/ops.spade:255,29" *) wire _e_2274; (* src = "/core/ops.spade:255,9" *) wire _e_2273; (* src = "/core/ops.spade:255,9" *) wire _e_1781; (* src = "src/main.spade:21,16" *) wire [3:0] _e_1774; assign _e_2156 = _e_2157_mut; assign _e_1733 = {_e_2156}; assign {_e_2157_mut} = _e_1733_mut; assign \clk_pll = _e_1733; assign _e_1733_mut = \clk_pll_wire_mut ; assign _e_2158 = _e_2159_mut; assign _e_1737 = {_e_2158}; assign {_e_2159_mut} = _e_1737_mut; assign \lock_pll = _e_1737; assign _e_1737_mut = \lock_pll_wire_mut ; wire \clk ; (* src = "src/main.spade:11,5" *) pll \pll_0 ( .clkin(\clk ), .init_clk(\clk ), .clkout0(\clk_pll_wire_mut ), .lock(\lock_pll_wire_mut ) ); assign _e_1746 = \counter == _e_1748; (* src = "src/main.spade:13,75" *) \core::ops::impl#77::wrapping_add[1533] \wrapping_add_0 ( .self_i(\counter ), .rhs_i(_e_1754), .output__(_e_1752) ); assign _e_1745 = (_e_1746 ? _e_1750 : _e_1752); always @(posedge \clk_pll ) \counter <= _e_1745; assign _e_1758 = \counter == _e_1760; assign _e_2242 = {\on }; assign _e_2241 = ~_e_2242; assign _e_1762 = _e_2241; assign _e_1757 = (_e_1758 ? _e_1762 : \on ); always @(posedge \clk_pll ) \on <= _e_1757; assign \tmds_clk_mut = \clk_pll ; assign _e_1769 = {_e_1772, _e_1771, _e_1770}; assign \tmds_mut = _e_1769; assign _e_2250 = {\on }; assign _e_2249 = ~_e_2250; assign _e_2248 = _e_2249; assign _e_2258 = {\on }; assign _e_2257 = ~_e_2258; assign _e_1777 = _e_2257; assign _e_2266 = {\on }; assign _e_2265 = ~_e_2266; assign _e_2264 = _e_2265; assign _e_2274 = {\lock_pll }; assign _e_2273 = ~_e_2274; assign _e_1781 = _e_2273; assign _e_1774 = {_e_1781, _e_2264, _e_1777, _e_2248}; assign \leds_mut = _e_1774; endmodule module \std::conv::impl#10::as_clock ( self_i, output__ ); input self_i; output wire output__; wire \self ; assign \self = self_i; wire _e_872; assign _e_872 = \self ; assign output__ = _e_872; endmodule module \std::conv::impl#10::as_uint ( self_i, output__ ); input self_i; output wire output__; wire \self ; assign \self = self_i; wire _e_876; assign _e_876 = \self ; assign output__ = _e_876; endmodule module \std::conv::impl#11::as_bool ( self_i, output__ ); input self_i; output wire output__; wire \self ; assign \self = self_i; wire _e_887; assign _e_887 = \self ; assign output__ = _e_887; endmodule module \std::conv::impl#12::as_bool ( self_i, output__ ); input self_i; output wire output__; wire \self ; assign \self = self_i; wire _e_895; assign _e_895 = \self ; assign output__ = _e_895; endmodule module \std::default::impl#17::hacky_default ( self_i, output__ ); input self_i; output wire output__; wire \self ; assign \self = self_i; localparam [0:0] _e_971 = 0; assign output__ = _e_971; endmodule module \std::default::impl#18::hacky_default ; endmodule module \core::ops::impl#77::wrapping_add[1533] ( self_i, rhs_i, output__ ); input [31:0] self_i; input [31:0] rhs_i; output wire [31:0] output__; wire [31:0] \self ; assign \self = self_i; wire [31:0] \rhs ; assign \rhs = rhs_i; (* src = "/core/ops.spade:166,62" *) wire [32:0] _e_1923; wire [32:0] \bits ; (* src = "/core/ops.spade:167,34" *) wire [31:0] _e_1928; wire [31:0] _e_1927; assign _e_1923 = \self + \rhs ; assign \bits = _e_1923; assign _e_1928 = \bits [31-:32]; assign _e_1927 = _e_1928; assign output__ = _e_1927; endmodule `default_nettype none