GowinSynthesis start
Running parser ...
Analyzing Verilog file '/work/RTL/spade.v'
Analyzing Verilog file '/work/RTL/pll.v'
Analyzing Verilog file '/work/RTL/gowin_pll_mod.v'
Compiling module 'main'("/work/RTL/spade.v":114)
Compiling module 'pll'("/work/RTL/gowin_pll_mod.v":2)
Compiling module 'Gowin_PLL_MOD'("/work/RTL/gowin_pll_mod.v":56)
Compiling module 'PLL_INIT(CLK_PERIOD=20,MULTI_FAC=15)'("/work/RTL/gowin_pll_mod.v":229)
WARN  (EX3791) : Expression size 5 truncated to fit in target size 4("/work/RTL/gowin_pll_mod.v":405)
WARN  (EX3791) : Expression size 18 truncated to fit in target size 17("/work/RTL/gowin_pll_mod.v":433)
Compiling module 'core::ops::impl#77::wrapping_add[1533]'("/work/RTL/spade.v":284)
NOTE  (EX0101) : Current top module is "main"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "/work/impl/gwsynthesis/build.vg" completed
[100%] Generate report file "/work/impl/gwsynthesis/build_syn.rpt.html" completed
GowinSynthesis finish