Reading netlist file: "/work/impl/gwsynthesis/build.vg"
Parsing netlist file "/work/impl/gwsynthesis/build.vg" completed
Processing netlist completed
Reading constraint file: "/work/pins.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
WARN  (TA1118) : the clock "clk"'s frequency does not match pll_0/u_pll/PLL_inst's param "FCLKIN = "50""
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
WARN  (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/work/impl/pnr/build.power.html" completed
Generate file "/work/impl/pnr/build.pin.html" completed
Generate file "/work/impl/pnr/build.rpt.html" completed
Generate file "/work/impl/pnr/build.rpt.txt" completed
Generate file "/work/impl/pnr/build.tr.html" completed
Thu Jun 18 20:00:32 2026