16 lines
254 B
Systemverilog
16 lines
254 B
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module NIddr_1(
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input clock,
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io_input_data,
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output io_output_data_0
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);
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IDDR iddrs_0 (
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.CLK (clock),
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.D (io_input_data),
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.Q0 (io_output_data_0),
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.Q1 (/* unused */)
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);
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endmodule
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