27 lines
623 B
Systemverilog
27 lines
623 B
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module RgmiiReset(
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input clock,
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reset,
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output io_ethernet_reset,
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input io_pll_locked
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);
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reg [1:0] state;
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reg timer;
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wire _GEN = state == 2'h0;
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wire _GEN_0 = state == 2'h1;
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always @(posedge clock) begin
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if (reset) begin
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state <= 2'h0;
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timer <= 1'h0;
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end
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else begin
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if (_GEN)
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state <= {1'h0, io_pll_locked};
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timer <= ~_GEN & (_GEN_0 ? timer - 1'h1 : state == 2'h2 ? timer - 1'h1 : timer);
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end
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end // always @(posedge)
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assign io_ethernet_reset = _GEN | _GEN_0 | state != 2'h2;
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endmodule
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