252 lines
6.9 KiB
Systemverilog
252 lines
6.9 KiB
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module Top(
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input clk,
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irst,
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output [3:0] leds,
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output txp,
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RGMII_GTXCLK,
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PHY_CLK,
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input RGMII_RXCK,
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RGMII_RXD_0,
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RGMII_RXD_1,
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RGMII_RXD_2,
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RGMII_RXD_3,
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RGMII_RXDV,
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output RGMII_RST_N,
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RGMII_TXEN
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);
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wire _uart_tx_io_data_ready;
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wire _uart_ce_io_output_ce;
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wire _iddr_dv_io_output_data_0;
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wire [3:0] _iddr_io_output_data_0;
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wire [3:0] _iddr_io_output_data_1;
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wire _byte_queue_read_io_deq_valid;
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wire [7:0] _byte_queue_read_io_deq_bits;
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wire _ethernet_clock_lock;
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wire _rgmii_rxdv_dly2_DO;
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wire _rgmii_rxdv_dly_DO;
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wire _rgmii_rxd_dly2_3_DO;
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wire _rgmii_rxd_dly1_3_DO;
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wire _rgmii_rxd_dly2_2_DO;
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wire _rgmii_rxd_dly1_2_DO;
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wire _rgmii_rxd_dly2_1_DO;
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wire _rgmii_rxd_dly1_1_DO;
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wire _rgmii_rxd_dly2_DO;
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wire _rgmii_rxd_dly1_DO;
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wire [7:0] normal_byte = {_iddr_io_output_data_1, _iddr_io_output_data_0};
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reg [3:0] skewed_byte_REG;
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wire [7:0] skewed_byte = {_iddr_io_output_data_0, skewed_byte_REG};
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reg normal_preamble_seen;
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reg skewed_preamble_seen;
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reg [1:0] ethernet_state;
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wire _GEN = ethernet_state == 2'h0;
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wire [3:0][7:0] _GEN_0 = {{8'h0}, {skewed_byte}, {normal_byte}, {8'h0}};
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always @(posedge RGMII_RXCK) begin
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skewed_byte_REG <= _iddr_io_output_data_1;
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if (~irst) begin
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normal_preamble_seen <= 1'h0;
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skewed_preamble_seen <= 1'h0;
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ethernet_state <= 2'h0;
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end
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else begin
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automatic logic _GEN_1;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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_GEN_1 = normal_preamble_seen & normal_byte == 8'hD5;
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_GEN_2 = _GEN & _iddr_dv_io_output_data_0;
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_GEN_3 = skewed_preamble_seen & skewed_byte == 8'hD5;
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if (_GEN_2) begin
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normal_preamble_seen <= ~_GEN_1 & (normal_byte == 8'h55 | normal_preamble_seen);
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skewed_preamble_seen <= ~_GEN_3 & (skewed_byte == 8'h55 | skewed_preamble_seen);
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end
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if (_iddr_dv_io_output_data_0) begin
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if (_GEN_2) begin
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if (_GEN_3)
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ethernet_state <= 2'h2;
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else if (_GEN_1)
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ethernet_state <= 2'h1;
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end
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end
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else
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ethernet_state <= 2'h0;
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end
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end // always @(posedge)
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(255),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxd_dly1 (
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.DI (RGMII_RXD_0),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxd_dly1_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(52),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxd_dly2 (
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.DI (_rgmii_rxd_dly1_DO),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxd_dly2_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(255),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxd_dly1_1 (
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.DI (RGMII_RXD_1),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxd_dly1_1_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(52),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxd_dly2_1 (
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.DI (_rgmii_rxd_dly1_1_DO),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxd_dly2_1_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(255),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxd_dly1_2 (
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.DI (RGMII_RXD_2),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxd_dly1_2_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(52),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxd_dly2_2 (
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.DI (_rgmii_rxd_dly1_2_DO),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxd_dly2_2_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(255),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxd_dly1_3 (
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.DI (RGMII_RXD_3),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxd_dly1_3_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(52),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxd_dly2_3 (
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.DI (_rgmii_rxd_dly1_3_DO),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxd_dly2_3_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(255),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxdv_dly (
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.DI (RGMII_RXDV),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxdv_dly_DO),
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.DF (/* unused */)
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);
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IODELAY #(
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.ADAPT_EN("FALSE"),
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.C_STATIC_DLY(200),
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.DYN_DLY_EN("FALSE")
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) rgmii_rxdv_dly2 (
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.DI (_rgmii_rxdv_dly_DO),
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.SDTAP (1'h0),
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.DLYSTEP (8'h0),
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.VALUE (1'h0),
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.DO (_rgmii_rxdv_dly2_DO),
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.DF (/* unused */)
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);
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ether_pll ethernet_clock (
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.clkin (clk),
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.init_clk (clk),
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.clkout0 (RGMII_GTXCLK),
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.clkout1 (PHY_CLK),
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.lock (_ethernet_clock_lock)
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);
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AysncFifo byte_queue (
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.write_io_clk (RGMII_RXCK),
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.write_io_enq_valid
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(~(~_iddr_dv_io_output_data_0 | _GEN)
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& (ethernet_state == 2'h1 | ethernet_state == 2'h2)),
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.write_io_enq_bits (_GEN_0[ethernet_state]),
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.read_io_clk (clk),
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.read_io_deq_ready (_uart_tx_io_data_ready),
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.read_io_deq_valid (_byte_queue_read_io_deq_valid),
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.read_io_deq_bits (_byte_queue_read_io_deq_bits)
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);
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NIddr iddr (
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.clock (RGMII_RXCK),
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.io_input_data
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({_rgmii_rxd_dly2_3_DO,
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_rgmii_rxd_dly2_2_DO,
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_rgmii_rxd_dly2_1_DO,
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_rgmii_rxd_dly2_DO}),
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.io_output_data_0 (_iddr_io_output_data_0),
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.io_output_data_1 (_iddr_io_output_data_1)
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);
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NIddr_1 iddr_dv (
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.clock (RGMII_RXCK),
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.io_input_data (_rgmii_rxdv_dly2_DO),
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.io_output_data_0 (_iddr_dv_io_output_data_0)
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);
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RgmiiReset ethernet_reset (
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.clock (clk),
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.reset (~irst),
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.io_ethernet_reset (RGMII_RST_N),
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.io_pll_locked (_ethernet_clock_lock)
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);
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UartClockEnable uart_ce (
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.clock (clk),
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.reset (~irst),
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.io_output_ce (_uart_ce_io_output_ce)
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);
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UartTx uart_tx (
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.clock (clk),
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.reset (~irst),
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.io_data_ready (_uart_tx_io_data_ready),
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.io_data_valid (_byte_queue_read_io_deq_valid),
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.io_data_bits (_byte_queue_read_io_deq_bits),
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.io_signal (txp),
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.io_clock_enable (_uart_ce_io_output_ce)
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);
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assign leds = 4'h0;
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assign RGMII_TXEN = 1'h0;
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endmodule
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