63 lines
1.6 KiB
Verilog
63 lines
1.6 KiB
Verilog
module UartTx (
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clock,
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reset,
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io_data_ready,
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io_data_valid,
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io_data_bits,
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io_signal,
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io_clock_enable
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);
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input clock;
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input reset;
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output wire io_data_ready;
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input io_data_valid;
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input [7:0] io_data_bits;
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output wire io_signal;
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input io_clock_enable;
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reg [1:0] state;
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reg [7:0] data;
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reg data_waiting;
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reg [2:0] bit_counter;
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reg [7:0] stop_bit_wait;
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wire _GEN = state == 2'h0;
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wire _GEN_0 = state == 2'h1;
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wire _GEN_1 = state == 2'h2;
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wire [7:0] _io_signal_T = data >> bit_counter;
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always @(posedge clock) begin : sv2v_autoblock_1
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reg _GEN_2;
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_GEN_2 = ~data_waiting & io_data_valid;
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if (reset) begin
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state <= 2'h0;
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data_waiting <= 1'h0;
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stop_bit_wait <= 8'h00;
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end
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else begin : sv2v_autoblock_2
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reg _GEN_3;
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reg _GEN_4;
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reg _GEN_5;
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_GEN_5 = (_GEN | _GEN_0) | _GEN_1;
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_GEN_3 = stop_bit_wait == 8'h14;
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_GEN_4 = &state & _GEN_3;
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if (io_clock_enable) begin : sv2v_autoblock_3
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reg [7:0] _GEN_6;
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_GEN_6 = {(_GEN_4 ? 2'h0 : state), 1'h1, &bit_counter, 3'h4, data_waiting};
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state <= _GEN_6[state * 2+:2];
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end
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data_waiting <= ((~io_clock_enable | _GEN_5) | ~_GEN_4) & (_GEN_2 | data_waiting);
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if ((~io_clock_enable | _GEN_5) | ~(&state))
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;
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else
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stop_bit_wait <= (_GEN_3 ? 8'h00 : stop_bit_wait + 8'h01);
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end
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if (_GEN_2)
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data <= io_data_bits;
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if (io_clock_enable) begin : sv2v_autoblock_4
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reg [11:0] _GEN_7;
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_GEN_7 = {bit_counter, bit_counter + 3'h1, 3'h0, bit_counter};
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bit_counter <= _GEN_7[state * 3+:3];
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end
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end
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assign io_data_ready = ~data_waiting;
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assign io_signal = _GEN | (~_GEN_0 & (~_GEN_1 | _io_signal_T[0]));
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endmodule
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