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49c9e6315b971c7a4c253b9bf12ce89b1272c0ca
gowin-toolchain/RTL/gowin/pll.v
Albin Chaboissier 49c9e6315b gogogaga
2026-07-09 22:48:08 +02:00

811 lines
21 KiB
Verilog
Raw Blame History

`default_nettype wire
module normal_ra(
data_out,
addr,
clk,
ce,
rst
);
output reg [15:0] data_out;
input [19:0] addr;
input clk,ce,rst;
/* synthesis syn_ramstyle = "block_ram" */
reg [15:0] mem [614399:0] /* synthesis syn_ramstyle = "block_ram" */;
//reg [15:0] mem [2:0] /* synthesis syn_ramstyle = "block_ram" */;
initial begin
$readmemh("finger.mem", mem);
end
reg [19:0] reg_addr;
reg reg_ce;
always@(posedge clk) begin
reg_addr<=addr;
reg_ce<=ce;
if(rst) begin
reg_addr <= 0;
reg_ce <= 0;
data_out <= 0;
end
else if(reg_ce) begin
data_out <= mem[reg_addr];
end
end
endmodule
module oser10(
input [9:0] data,
input wire pclk,
input wire fclk,
input wire resetn,
output wire q
);
OSER10 uut(
.Q(q),
.D0(data[0]),
.D1(data[1]),
.D2(data[2]),
.D3(data[3]),
.D4(data[4]),
.D5(data[5]),
.D6(data[6]),
.D7(data[7]),
.D8(data[8]),
.D9(data[9]),
.PCLK(pclk),
.FCLK(fclk),
.RESET(resetn)
);
//defparam uut.GSREN="false";
//defparam uut.LSREN="true";
endmodule
module clkdiv(clkout, hclkin, resetn);
output clkout;
input hclkin;
input resetn;
wire gw_gnd;
assign gw_gnd = 1'b0;
CLKDIV clkdiv_inst (
.CLKOUT(clkout),
.HCLKIN(hclkin),
.RESETN(resetn),
.CALIB(gw_gnd)
);
defparam clkdiv_inst.DIV_MODE = "5";
endmodule //Gowin_CLKDIV
//Copyright (C)2014-2026 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//Tool Version: V1.9.12.02_SP2
//IP Version: 1.0
//Part Number: GW5AST-LV138PG484AC1/I0
//Device: GW5AST-138
//Device Version: C
//Created Time: Fri Jun 19 18:52:20 2026
module Gowin_PLL_MOD (lock, clkout0, clkin, reset, icpsel, lpfres, lpfcap);
output lock;
output clkout0;
input clkin;
input reset;
input [5:0] icpsel;
input [2:0] lpfres;
input [1:0] lpfcap;
wire clkout1;
wire clkout2;
wire clkout3;
wire clkout4;
wire clkout5;
wire clkout6;
wire clkfbout;
wire gw_vcc;
wire gw_gnd;
assign gw_vcc = 1'b1;
assign gw_gnd = 1'b0;
PLL PLL_inst (
.LOCK(lock),
.CLKOUT0(clkout0),
.CLKOUT1(clkout1),
.CLKOUT2(clkout2),
.CLKOUT3(clkout3),
.CLKOUT4(clkout4),
.CLKOUT5(clkout5),
.CLKOUT6(clkout6),
.CLKFBOUT(clkfbout),
.CLKIN(clkin),
.CLKFB(gw_gnd),
.RESET(reset),
.PLLPWD(gw_gnd),
.RESET_I(gw_gnd),
.RESET_O(gw_gnd),
.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL1({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL2({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL3({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL4({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL5({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL6({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT0({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT1({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT2({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT3({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ICPSEL(icpsel),
.LPFRES(lpfres),
.LPFCAP(lpfcap),
.PSSEL({gw_gnd,gw_gnd,gw_gnd}),
.PSDIR(gw_gnd),
.PSPULSE(gw_gnd),
.ENCLK0(gw_vcc),
.ENCLK1(gw_vcc),
.ENCLK2(gw_vcc),
.ENCLK3(gw_vcc),
.ENCLK4(gw_vcc),
.ENCLK5(gw_vcc),
.ENCLK6(gw_vcc),
.SSCPOL(gw_gnd),
.SSCON(gw_gnd),
.SSCMDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.SSCMDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd})
);
defparam PLL_inst.FCLKIN = "50";
defparam PLL_inst.IDIV_SEL = 1;
defparam PLL_inst.FBDIV_SEL = 3;
defparam PLL_inst.ODIV0_SEL = 6;
defparam PLL_inst.ODIV1_SEL = 8;
defparam PLL_inst.ODIV2_SEL = 8;
defparam PLL_inst.ODIV3_SEL = 8;
defparam PLL_inst.ODIV4_SEL = 8;
defparam PLL_inst.ODIV5_SEL = 8;
defparam PLL_inst.ODIV6_SEL = 8;
defparam PLL_inst.MDIV_SEL = 5;
defparam PLL_inst.MDIV_FRAC_SEL = 2;
defparam PLL_inst.ODIV0_FRAC_SEL = 2;
defparam PLL_inst.CLKOUT0_EN = "TRUE";
defparam PLL_inst.CLKOUT1_EN = "FALSE";
defparam PLL_inst.CLKOUT2_EN = "FALSE";
defparam PLL_inst.CLKOUT3_EN = "FALSE";
defparam PLL_inst.CLKOUT4_EN = "FALSE";
defparam PLL_inst.CLKOUT5_EN = "FALSE";
defparam PLL_inst.CLKOUT6_EN = "FALSE";
defparam PLL_inst.CLKFB_SEL = "INTERNAL";
defparam PLL_inst.CLKOUT0_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT1_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT2_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT3_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT0_DT_STEP = 0;
defparam PLL_inst.CLKOUT1_DT_STEP = 0;
defparam PLL_inst.CLKOUT2_DT_STEP = 0;
defparam PLL_inst.CLKOUT3_DT_STEP = 0;
defparam PLL_inst.CLK0_IN_SEL = 1'b0;
defparam PLL_inst.CLK0_OUT_SEL = 1'b0;
defparam PLL_inst.CLK1_IN_SEL = 1'b0;
defparam PLL_inst.CLK1_OUT_SEL = 1'b0;
defparam PLL_inst.CLK2_IN_SEL = 1'b0;
defparam PLL_inst.CLK2_OUT_SEL = 1'b0;
defparam PLL_inst.CLK3_IN_SEL = 1'b0;
defparam PLL_inst.CLK3_OUT_SEL = 1'b0;
defparam PLL_inst.CLK4_IN_SEL = 2'b00;
defparam PLL_inst.CLK4_OUT_SEL = 1'b0;
defparam PLL_inst.CLK5_IN_SEL = 1'b0;
defparam PLL_inst.CLK5_OUT_SEL = 1'b0;
defparam PLL_inst.CLK6_IN_SEL = 1'b0;
defparam PLL_inst.CLK6_OUT_SEL = 1'b0;
defparam PLL_inst.DYN_DPA_EN = "FALSE";
defparam PLL_inst.CLKOUT0_PE_COARSE = 0;
defparam PLL_inst.CLKOUT0_PE_FINE = 0;
defparam PLL_inst.CLKOUT1_PE_COARSE = 0;
defparam PLL_inst.CLKOUT1_PE_FINE = 0;
defparam PLL_inst.CLKOUT2_PE_COARSE = 0;
defparam PLL_inst.CLKOUT2_PE_FINE = 0;
defparam PLL_inst.CLKOUT3_PE_COARSE = 0;
defparam PLL_inst.CLKOUT3_PE_FINE = 0;
defparam PLL_inst.CLKOUT4_PE_COARSE = 0;
defparam PLL_inst.CLKOUT4_PE_FINE = 0;
defparam PLL_inst.CLKOUT5_PE_COARSE = 0;
defparam PLL_inst.CLKOUT5_PE_FINE = 0;
defparam PLL_inst.CLKOUT6_PE_COARSE = 0;
defparam PLL_inst.CLKOUT6_PE_FINE = 0;
defparam PLL_inst.DYN_PE0_SEL = "FALSE";
defparam PLL_inst.DYN_PE1_SEL = "FALSE";
defparam PLL_inst.DYN_PE2_SEL = "FALSE";
defparam PLL_inst.DYN_PE3_SEL = "FALSE";
defparam PLL_inst.DYN_PE4_SEL = "FALSE";
defparam PLL_inst.DYN_PE5_SEL = "FALSE";
defparam PLL_inst.DYN_PE6_SEL = "FALSE";
defparam PLL_inst.DE0_EN = "FALSE";
defparam PLL_inst.DE1_EN = "FALSE";
defparam PLL_inst.DE2_EN = "FALSE";
defparam PLL_inst.DE3_EN = "FALSE";
defparam PLL_inst.DE4_EN = "FALSE";
defparam PLL_inst.DE5_EN = "FALSE";
defparam PLL_inst.DE6_EN = "FALSE";
defparam PLL_inst.RESET_I_EN = "FALSE";
defparam PLL_inst.RESET_O_EN = "FALSE";
defparam PLL_inst.ICP_SEL = 6'bXXXXXX;
defparam PLL_inst.LPF_RES = 3'bXXX;
defparam PLL_inst.LPF_CAP = 2'b00;
defparam PLL_inst.SSC_EN = "FALSE";
defparam PLL_inst.DYN_IDIV_SEL = "FALSE";
defparam PLL_inst.DYN_FBDIV_SEL = "FALSE";
defparam PLL_inst.DYN_MDIV_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV0_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV1_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV2_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV3_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV4_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV5_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV6_SEL = "FALSE";
defparam PLL_inst.DYN_DT0_SEL = "FALSE";
defparam PLL_inst.DYN_DT1_SEL = "FALSE";
defparam PLL_inst.DYN_DT2_SEL = "FALSE";
defparam PLL_inst.DYN_DT3_SEL = "FALSE";
defparam PLL_inst.DYN_ICP_SEL = "TRUE";
defparam PLL_inst.DYN_LPF_SEL = "TRUE";
endmodule //Gowin_PLL_MOD
module pll(
clkin,
init_clk,
clkout0
);
input clkin;
input init_clk;
output clkout0;
wire lock;
wire [5:0] icpsel;
wire [2:0] lpfres;
wire pll_lock;
wire pll_rst;
Gowin_PLL_MOD u_pll(
.clkout0(clkout0),
.lock(pll_lock),
.clkin(clkin),
.reset(pll_rst),
.icpsel(icpsel),
.lpfres(lpfres),
.lpfcap(2'b00)
);
PLL_INIT u_pll_init(
.CLKIN(init_clk),
.I_RST(1'b0),
.O_RST(pll_rst),
.PLLLOCK(pll_lock),
.O_LOCK(lock),
.ICPSEL(icpsel),
.LPFRES(lpfres)
);
defparam u_pll_init.CLK_PERIOD = 20;
defparam u_pll_init.MULTI_FAC = 15;
endmodule
`timescale 1ns/1ns
module PLL_INIT
#(
parameter CLK_PERIOD = 50,
parameter MULTI_FAC = 30
)
(
input CLKIN,
input I_RST,
input PLLLOCK,
output O_RST,
output [5:0] ICPSEL,
output [2:0] LPFRES,
output O_LOCK
);
localparam WAIT_TIME = 'd2000_000;
localparam WAIT_CNT = (WAIT_TIME + CLK_PERIOD - 1) / CLK_PERIOD;
localparam WAIT_WIDTH = $clog2(WAIT_CNT + 1);
reg [WAIT_WIDTH-1:0] waitcnt = 'd0;
reg [3:0] RomAddr = 'd0;
reg [15:0] Rom [15:0];
reg [15:0] RomDreg ='d0;
wire [5:0] Regicp = RomDreg[5:0];
wire [2:0] Regres = RomDreg[10:8];
reg Waitlock = 'd0;
reg [7:0] locksig = 8'b0000_0000;
reg laststep = 1'b0;
wire validsig = RomDreg[12];
reg [1:0]enable_r = 2'b00;
wire Enable = enable_r[1];
always @(posedge CLKIN or posedge I_RST)
begin
if (I_RST)
enable_r <= 2'b00;
else
begin
enable_r <= {enable_r[0], 1'b1};
end
end
always @(posedge CLKIN or negedge Enable)
begin
if (Enable == 1'b0)
begin
RomDreg <= 16'h0000;
Rom[00] <= 16'h1400; //1
Rom[01] <= (MULTI_FAC > 34) ? 16'h1401
: (MULTI_FAC > 16) ? 16'h1400
: 16'h1400; //2
Rom[02] <= (MULTI_FAC > 34) ? 16'h1501
: (MULTI_FAC > 16) ? 16'h1500
: 16'h1500; //3
Rom[03] <= (MULTI_FAC > 34) ? 16'h1503
: (MULTI_FAC > 16) ? 16'h1501
: 16'h1500; //4
Rom[04] <= (MULTI_FAC > 34) ? 16'h1507
: (MULTI_FAC > 16) ? 16'h1503
: 16'h1501; //5
Rom[05] <= (MULTI_FAC > 34) ? 16'h0605
: (MULTI_FAC > 16) ? 16'h0602
: 16'h0601; //6
Rom[06] <= 16'h0000; //over
Rom[07] <= (MULTI_FAC > 34) ? 16'h1402
: (MULTI_FAC > 16) ? 16'h1401
: 16'h1400; //2.5
Rom[08] <= (MULTI_FAC > 34) ? 16'h1502
: (MULTI_FAC > 16) ? 16'h1501
: 16'h1500; //3.5
Rom[09] <= (MULTI_FAC > 34) ? 16'h1504
: (MULTI_FAC > 16) ? 16'h1502
: 16'h1501; //4.5
Rom[10] <= (MULTI_FAC > 34) ? 16'h1603
: (MULTI_FAC > 16) ? 16'h1601
: 16'h1600; //5.5
Rom[11] <= 16'h1400; //1.5
Rom[12] <= 16'h0000;
Rom[13] <= 16'h0000;
Rom[14] <= 16'h0000;
Rom[15] <= 16'h0000;
end
else
RomDreg <= Rom[RomAddr[3:0]];
end
reg [3:0]RomAddrVld = 'd0;
always @ (*) begin
casex (locksig[5:0])
6'b111_111 : RomAddrVld = 4'd8;
6'b011_111 : RomAddrVld = 4'd8;
6'b111_110 : RomAddrVld = 4'd8;
6'b111_10x : RomAddrVld = 4'd9;
6'bx01_111 : RomAddrVld = 4'd7;
6'b011_110 : RomAddrVld = 4'd8;
6'bxx0_111 : RomAddrVld = 4'd1;
6'bx01_110 : RomAddrVld = 4'd2;
6'b011_10x : RomAddrVld = 4'd3;
6'b111_0xx : RomAddrVld = 4'd4;
6'bxxx_011 : RomAddrVld = 4'd1;
6'bxx0_110 : RomAddrVld = 4'd7;
6'bx01_100 : RomAddrVld = 4'd8;
6'b011_000 : RomAddrVld = 4'd9;
6'b110_000 : RomAddrVld = 4'd10;
6'bxxx_x01 : RomAddrVld = 4'd0;
6'bxxx_010 : RomAddrVld = 4'd1;
6'bxx0_100 : RomAddrVld = 4'd2;
6'bx01_000 : RomAddrVld = 4'd3;
6'b010_000 : RomAddrVld = 4'd4;
6'b100_000 : RomAddrVld = 4'd5;
6'b000_000 : RomAddrVld = 4'd8;
default : RomAddrVld = 4'd8;
endcase
end
reg [3:0]state='d0;
localparam IDLE = 4'd0;
localparam STATE1 = 4'd1;
localparam STATE2 = 4'd2;
localparam STATE3 = 4'd3;
localparam STATE4 = 4'd4;
localparam STATE5 = 4'd5;
localparam STATE6 = 4'd6;
localparam STATE7 = 4'd7;
always @(posedge CLKIN or negedge Enable)
begin
if (Enable == 1'b0)
begin
state <= IDLE;
RomAddr<=4'b0000;
laststep <= 1'b0;
end
else
begin
case (state)
IDLE:
begin
state<=STATE1;
end
STATE1:
begin
state<=STATE2;
end
STATE2:
begin
if (laststep==1'b1)
state<=STATE7;
else
state<=STATE3;
end
STATE3:
begin
if (Waitlock==1'b1)
state<=STATE4;
else
state<= STATE3;
end
STATE4:
begin
state<=STATE5;
end
STATE5:
begin
if (validsig==1'b1)
begin
RomAddr <= RomAddr + 1;
state <= STATE1;
end
else if (validsig==1'b0 && laststep==1'b0)
state <= STATE6;
end
STATE6:
begin
RomAddr <= RomAddrVld;
laststep <= 1'b1;
state <= STATE1;
end
STATE7:
begin
state<=STATE7;
end
default: state<=IDLE;
endcase
end
end
always @(posedge CLKIN)
begin
Waitlock <= (&waitcnt == 1'b1) ? 1'b1 : 1'b0;
waitcnt <= (state==STATE3) ? (waitcnt+1) : 'd0;
if (~Enable) locksig <= 8'b0000_0000;
else if (state==STATE4) locksig[RomAddr[3:0]] <= PLLLOCK;
end
assign ICPSEL = Regicp;
assign LPFRES = Regres;
assign O_RST = (~Enable) || (state==STATE2) ? 1'b1 : 1'b0;
assign O_LOCK = (state==STATE7) ? PLLLOCK : 1'b0;
endmodule
module ether_pll(
clkin,
init_clk,
clkout0,
clkout1,
lock
);
input clkin;
input init_clk;
output clkout0;
output clkout1;
output lock;
wire [5:0] icpsel;
wire [2:0] lpfres;
wire pll_lock;
wire pll_rst;
Gowin_PLL_MOD_ether u_pll(
.clkout1(clkout1),
.clkout0(clkout0),
.lock(pll_lock),
.clkin(clkin),
.reset(pll_rst),
.icpsel(icpsel),
.lpfres(lpfres),
.lpfcap(2'b00)
);
PLL_INIT u_pll_init(
.CLKIN(init_clk),
.I_RST(1'b0),
.O_RST(pll_rst),
.PLLLOCK(pll_lock),
.O_LOCK(lock),
.ICPSEL(icpsel),
.LPFRES(lpfres)
);
defparam u_pll_init.CLK_PERIOD = 20;
defparam u_pll_init.MULTI_FAC = 15;
endmodule
module Gowin_PLL_MOD_ether (lock, clkout0, clkout1, clkin, reset, icpsel, lpfres, lpfcap);
output lock;
output clkout0;
output clkout1;
input clkin;
input reset;
input [5:0] icpsel;
input [2:0] lpfres;
input [1:0] lpfcap;
wire clkout2;
wire clkout3;
wire clkout4;
wire clkout5;
wire clkout6;
wire clkfbout;
wire gw_vcc;
wire gw_gnd;
assign gw_vcc = 1'b1;
assign gw_gnd = 1'b0;
PLL PLL_inst (
.LOCK(lock),
.CLKOUT0(clkout0),
.CLKOUT1(clkout1),
.CLKOUT2(clkout2),
.CLKOUT3(clkout3),
.CLKOUT4(clkout4),
.CLKOUT5(clkout5),
.CLKOUT6(clkout6),
.CLKFBOUT(clkfbout),
.CLKIN(clkin),
.CLKFB(gw_gnd),
.RESET(reset),
.PLLPWD(gw_gnd),
.RESET_I(gw_gnd),
.RESET_O(gw_gnd),
.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL1({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL2({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL3({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL4({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL5({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL6({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT0({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT1({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT2({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT3({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ICPSEL(icpsel),
.LPFRES(lpfres),
.LPFCAP(lpfcap),
.PSSEL({gw_gnd,gw_gnd,gw_gnd}),
.PSDIR(gw_gnd),
.PSPULSE(gw_gnd),
.ENCLK0(gw_vcc),
.ENCLK1(gw_vcc),
.ENCLK2(gw_vcc),
.ENCLK3(gw_vcc),
.ENCLK4(gw_vcc),
.ENCLK5(gw_vcc),
.ENCLK6(gw_vcc),
.SSCPOL(gw_gnd),
.SSCON(gw_gnd),
.SSCMDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.SSCMDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd})
);
defparam PLL_inst.FCLKIN = "50";
defparam PLL_inst.IDIV_SEL = 1;
defparam PLL_inst.FBDIV_SEL = 1;
defparam PLL_inst.ODIV0_SEL = 6;
defparam PLL_inst.ODIV1_SEL = 30;
defparam PLL_inst.ODIV2_SEL = 8;
defparam PLL_inst.ODIV3_SEL = 8;
defparam PLL_inst.ODIV4_SEL = 8;
defparam PLL_inst.ODIV5_SEL = 8;
defparam PLL_inst.ODIV6_SEL = 8;
defparam PLL_inst.MDIV_SEL = 15;
defparam PLL_inst.MDIV_FRAC_SEL = 0;
defparam PLL_inst.ODIV0_FRAC_SEL = 0;
defparam PLL_inst.CLKOUT0_EN = "TRUE";
defparam PLL_inst.CLKOUT1_EN = "TRUE";
defparam PLL_inst.CLKOUT2_EN = "FALSE";
defparam PLL_inst.CLKOUT3_EN = "FALSE";
defparam PLL_inst.CLKOUT4_EN = "FALSE";
defparam PLL_inst.CLKOUT5_EN = "FALSE";
defparam PLL_inst.CLKOUT6_EN = "FALSE";
defparam PLL_inst.CLKFB_SEL = "INTERNAL";
defparam PLL_inst.CLKOUT0_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT1_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT2_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT3_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT0_DT_STEP = 0;
defparam PLL_inst.CLKOUT1_DT_STEP = 0;
defparam PLL_inst.CLKOUT2_DT_STEP = 0;
defparam PLL_inst.CLKOUT3_DT_STEP = 0;
defparam PLL_inst.CLK0_IN_SEL = 1'b0;
defparam PLL_inst.CLK0_OUT_SEL = 1'b0;
defparam PLL_inst.CLK1_IN_SEL = 1'b0;
defparam PLL_inst.CLK1_OUT_SEL = 1'b0;
defparam PLL_inst.CLK2_IN_SEL = 1'b0;
defparam PLL_inst.CLK2_OUT_SEL = 1'b0;
defparam PLL_inst.CLK3_IN_SEL = 1'b0;
defparam PLL_inst.CLK3_OUT_SEL = 1'b0;
defparam PLL_inst.CLK4_IN_SEL = 2'b00;
defparam PLL_inst.CLK4_OUT_SEL = 1'b0;
defparam PLL_inst.CLK5_IN_SEL = 1'b0;
defparam PLL_inst.CLK5_OUT_SEL = 1'b0;
defparam PLL_inst.CLK6_IN_SEL = 1'b0;
defparam PLL_inst.CLK6_OUT_SEL = 1'b0;
defparam PLL_inst.DYN_DPA_EN = "FALSE";
defparam PLL_inst.CLKOUT0_PE_COARSE = 0;
defparam PLL_inst.CLKOUT0_PE_FINE = 0;
defparam PLL_inst.CLKOUT1_PE_COARSE = 0;
defparam PLL_inst.CLKOUT1_PE_FINE = 0;
defparam PLL_inst.CLKOUT2_PE_COARSE = 0;
defparam PLL_inst.CLKOUT2_PE_FINE = 0;
defparam PLL_inst.CLKOUT3_PE_COARSE = 0;
defparam PLL_inst.CLKOUT3_PE_FINE = 0;
defparam PLL_inst.CLKOUT4_PE_COARSE = 0;
defparam PLL_inst.CLKOUT4_PE_FINE = 0;
defparam PLL_inst.CLKOUT5_PE_COARSE = 0;
defparam PLL_inst.CLKOUT5_PE_FINE = 0;
defparam PLL_inst.CLKOUT6_PE_COARSE = 0;
defparam PLL_inst.CLKOUT6_PE_FINE = 0;
defparam PLL_inst.DYN_PE0_SEL = "FALSE";
defparam PLL_inst.DYN_PE1_SEL = "FALSE";
defparam PLL_inst.DYN_PE2_SEL = "FALSE";
defparam PLL_inst.DYN_PE3_SEL = "FALSE";
defparam PLL_inst.DYN_PE4_SEL = "FALSE";
defparam PLL_inst.DYN_PE5_SEL = "FALSE";
defparam PLL_inst.DYN_PE6_SEL = "FALSE";
defparam PLL_inst.DE0_EN = "FALSE";
defparam PLL_inst.DE1_EN = "FALSE";
defparam PLL_inst.DE2_EN = "FALSE";
defparam PLL_inst.DE3_EN = "FALSE";
defparam PLL_inst.DE4_EN = "FALSE";
defparam PLL_inst.DE5_EN = "FALSE";
defparam PLL_inst.DE6_EN = "FALSE";
defparam PLL_inst.RESET_I_EN = "FALSE";
defparam PLL_inst.RESET_O_EN = "FALSE";
defparam PLL_inst.ICP_SEL = 6'bXXXXXX;
defparam PLL_inst.LPF_RES = 3'bXXX;
defparam PLL_inst.LPF_CAP = 2'b00;
defparam PLL_inst.SSC_EN = "FALSE";
defparam PLL_inst.DYN_IDIV_SEL = "FALSE";
defparam PLL_inst.DYN_FBDIV_SEL = "FALSE";
defparam PLL_inst.DYN_MDIV_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV0_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV1_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV2_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV3_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV4_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV5_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV6_SEL = "FALSE";
defparam PLL_inst.DYN_DT0_SEL = "FALSE";
defparam PLL_inst.DYN_DT1_SEL = "FALSE";
defparam PLL_inst.DYN_DT2_SEL = "FALSE";
defparam PLL_inst.DYN_DT3_SEL = "FALSE";
defparam PLL_inst.DYN_ICP_SEL = "TRUE";
defparam PLL_inst.DYN_LPF_SEL = "TRUE";
endmodule //Gowin_PLL_MOD
module gowin_ddr(
din,
clk,
q
)
;
input [7:0] din;
input clk;
output [3:0] q;
wire \oddr_gen[0].oddr_inst_1_Q1 ;
wire \oddr_gen[1].oddr_inst_1_Q1 ;
wire \oddr_gen[2].oddr_inst_1_Q1 ;
wire \oddr_gen[3].oddr_inst_1_Q1 ;
wire VCC;
wire GND;
ODDR \oddr_gen[0].oddr_inst (
.Q0(q[0]),
.Q1(\oddr_gen[0].oddr_inst_1_Q1 ),
.D0(din[0]),
.D1(din[4]),
.TX(GND),
.CLK(clk)
);
ODDR \oddr_gen[1].oddr_inst (
.Q0(q[1]),
.Q1(\oddr_gen[1].oddr_inst_1_Q1 ),
.D0(din[1]),
.D1(din[5]),
.TX(GND),
.CLK(clk)
);
ODDR \oddr_gen[2].oddr_inst (
.Q0(q[2]),
.Q1(\oddr_gen[2].oddr_inst_1_Q1 ),
.D0(din[2]),
.D1(din[6]),
.TX(GND),
.CLK(clk)
);
ODDR \oddr_gen[3].oddr_inst (
.Q0(q[3]),
.Q1(\oddr_gen[3].oddr_inst_1_Q1 ),
.D0(din[3]),
.D1(din[7]),
.TX(GND),
.CLK(clk)
);
VCC VCC_cZ (
.V(VCC)
);
GND GND_cZ (
.G(GND)
);
GSR GSR (
.GSRI(VCC)
);
endmodule /* Gowin_DDR */
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