blinky
This commit is contained in:
446
RTL/gowin_pll_mod.v
Normal file
446
RTL/gowin_pll_mod.v
Normal file
@ -0,0 +1,446 @@
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`default_nettype wire
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module pll(
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clkin,
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init_clk,
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clkout0,
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lock
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);
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input clkin;
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input init_clk;
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output clkout0;
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output lock;
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wire [5:0] icpsel;
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wire [2:0] lpfres;
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wire pll_lock;
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wire pll_rst;
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Gowin_PLL_MOD u_pll(
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.clkout0(clkout0),
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.lock(pll_lock),
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.clkin(clkin),
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.reset(pll_rst),
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.icpsel(icpsel),
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.lpfres(lpfres),
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.lpfcap(2'b00)
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);
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PLL_INIT u_pll_init(
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.CLKIN(init_clk),
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.I_RST(1'b0),
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.O_RST(pll_rst),
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.PLLLOCK(pll_lock),
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.O_LOCK(lock),
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.ICPSEL(icpsel),
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.LPFRES(lpfres)
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);
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defparam u_pll_init.CLK_PERIOD = 20;
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defparam u_pll_init.MULTI_FAC = 15;
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endmodule
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//Copyright (C)2014-2026 Gowin Semiconductor Corporation.
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//All rights reserved.
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//File Title: IP file
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//Tool Version: V1.9.12.02_SP2
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//IP Version: 1.0
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//Part Number: GW5AST-LV138PG484AC1/I0
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//Device: GW5AST-138
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//Device Version: C
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//Created Time: Thu Jun 18 20:59:31 2026
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module Gowin_PLL_MOD (lock, clkout0, clkin, reset, icpsel, lpfres, lpfcap);
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output lock;
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output clkout0;
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input clkin;
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input reset;
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input [5:0] icpsel;
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input [2:0] lpfres;
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input [1:0] lpfcap;
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wire clkout1;
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wire clkout2;
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wire clkout3;
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wire clkout4;
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wire clkout5;
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wire clkout6;
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wire clkfbout;
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wire gw_vcc;
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wire gw_gnd;
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assign gw_vcc = 1'b1;
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assign gw_gnd = 1'b0;
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PLL PLL_inst (
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.LOCK(lock),
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.CLKOUT0(clkout0),
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.CLKOUT1(clkout1),
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.CLKOUT2(clkout2),
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.CLKOUT3(clkout3),
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.CLKOUT4(clkout4),
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.CLKOUT5(clkout5),
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.CLKOUT6(clkout6),
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.CLKFBOUT(clkfbout),
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.CLKIN(clkin),
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.CLKFB(gw_gnd),
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.RESET(reset),
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.PLLPWD(gw_gnd),
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.RESET_I(gw_gnd),
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.RESET_O(gw_gnd),
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.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.MDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.MDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL0({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL0_FRAC({gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL1({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL2({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL3({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL4({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL5({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL6({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.DT0({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.DT1({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.DT2({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.DT3({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ICPSEL(icpsel),
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.LPFRES(lpfres),
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.LPFCAP(lpfcap),
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.PSSEL({gw_gnd,gw_gnd,gw_gnd}),
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.PSDIR(gw_gnd),
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.PSPULSE(gw_gnd),
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.ENCLK0(gw_vcc),
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.ENCLK1(gw_vcc),
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.ENCLK2(gw_vcc),
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.ENCLK3(gw_vcc),
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.ENCLK4(gw_vcc),
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.ENCLK5(gw_vcc),
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.ENCLK6(gw_vcc),
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.SSCPOL(gw_gnd),
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.SSCON(gw_gnd),
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.SSCMDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.SSCMDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd})
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);
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defparam PLL_inst.FCLKIN = "50";
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defparam PLL_inst.IDIV_SEL = 1;
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defparam PLL_inst.FBDIV_SEL = 3;
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defparam PLL_inst.ODIV0_SEL = 31;
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defparam PLL_inst.ODIV1_SEL = 8;
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defparam PLL_inst.ODIV2_SEL = 8;
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defparam PLL_inst.ODIV3_SEL = 8;
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defparam PLL_inst.ODIV4_SEL = 8;
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defparam PLL_inst.ODIV5_SEL = 8;
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defparam PLL_inst.ODIV6_SEL = 8;
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defparam PLL_inst.MDIV_SEL = 5;
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defparam PLL_inst.MDIV_FRAC_SEL = 2;
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defparam PLL_inst.ODIV0_FRAC_SEL = 2;
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defparam PLL_inst.CLKOUT0_EN = "TRUE";
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defparam PLL_inst.CLKOUT1_EN = "FALSE";
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defparam PLL_inst.CLKOUT2_EN = "FALSE";
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defparam PLL_inst.CLKOUT3_EN = "FALSE";
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defparam PLL_inst.CLKOUT4_EN = "FALSE";
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defparam PLL_inst.CLKOUT5_EN = "FALSE";
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defparam PLL_inst.CLKOUT6_EN = "FALSE";
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defparam PLL_inst.CLKFB_SEL = "INTERNAL";
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defparam PLL_inst.CLKOUT0_DT_DIR = 1'b1;
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defparam PLL_inst.CLKOUT1_DT_DIR = 1'b1;
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defparam PLL_inst.CLKOUT2_DT_DIR = 1'b1;
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defparam PLL_inst.CLKOUT3_DT_DIR = 1'b1;
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defparam PLL_inst.CLKOUT0_DT_STEP = 0;
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defparam PLL_inst.CLKOUT1_DT_STEP = 0;
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defparam PLL_inst.CLKOUT2_DT_STEP = 0;
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defparam PLL_inst.CLKOUT3_DT_STEP = 0;
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defparam PLL_inst.CLK0_IN_SEL = 1'b0;
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defparam PLL_inst.CLK0_OUT_SEL = 1'b0;
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defparam PLL_inst.CLK1_IN_SEL = 1'b0;
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defparam PLL_inst.CLK1_OUT_SEL = 1'b0;
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defparam PLL_inst.CLK2_IN_SEL = 1'b0;
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defparam PLL_inst.CLK2_OUT_SEL = 1'b0;
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defparam PLL_inst.CLK3_IN_SEL = 1'b0;
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defparam PLL_inst.CLK3_OUT_SEL = 1'b0;
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defparam PLL_inst.CLK4_IN_SEL = 2'b00;
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defparam PLL_inst.CLK4_OUT_SEL = 1'b0;
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defparam PLL_inst.CLK5_IN_SEL = 1'b0;
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defparam PLL_inst.CLK5_OUT_SEL = 1'b0;
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defparam PLL_inst.CLK6_IN_SEL = 1'b0;
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defparam PLL_inst.CLK6_OUT_SEL = 1'b0;
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defparam PLL_inst.DYN_DPA_EN = "FALSE";
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defparam PLL_inst.CLKOUT0_PE_COARSE = 0;
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defparam PLL_inst.CLKOUT0_PE_FINE = 0;
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defparam PLL_inst.CLKOUT1_PE_COARSE = 0;
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defparam PLL_inst.CLKOUT1_PE_FINE = 0;
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defparam PLL_inst.CLKOUT2_PE_COARSE = 0;
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defparam PLL_inst.CLKOUT2_PE_FINE = 0;
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defparam PLL_inst.CLKOUT3_PE_COARSE = 0;
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defparam PLL_inst.CLKOUT3_PE_FINE = 0;
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defparam PLL_inst.CLKOUT4_PE_COARSE = 0;
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defparam PLL_inst.CLKOUT4_PE_FINE = 0;
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defparam PLL_inst.CLKOUT5_PE_COARSE = 0;
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defparam PLL_inst.CLKOUT5_PE_FINE = 0;
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defparam PLL_inst.CLKOUT6_PE_COARSE = 0;
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defparam PLL_inst.CLKOUT6_PE_FINE = 0;
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defparam PLL_inst.DYN_PE0_SEL = "FALSE";
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defparam PLL_inst.DYN_PE1_SEL = "FALSE";
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defparam PLL_inst.DYN_PE2_SEL = "FALSE";
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defparam PLL_inst.DYN_PE3_SEL = "FALSE";
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defparam PLL_inst.DYN_PE4_SEL = "FALSE";
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defparam PLL_inst.DYN_PE5_SEL = "FALSE";
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defparam PLL_inst.DYN_PE6_SEL = "FALSE";
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defparam PLL_inst.DE0_EN = "FALSE";
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defparam PLL_inst.DE1_EN = "FALSE";
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defparam PLL_inst.DE2_EN = "FALSE";
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defparam PLL_inst.DE3_EN = "FALSE";
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defparam PLL_inst.DE4_EN = "FALSE";
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defparam PLL_inst.DE5_EN = "FALSE";
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defparam PLL_inst.DE6_EN = "FALSE";
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defparam PLL_inst.RESET_I_EN = "FALSE";
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defparam PLL_inst.RESET_O_EN = "FALSE";
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defparam PLL_inst.ICP_SEL = 6'bXXXXXX;
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defparam PLL_inst.LPF_RES = 3'bXXX;
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defparam PLL_inst.LPF_CAP = 2'b00;
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defparam PLL_inst.SSC_EN = "FALSE";
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defparam PLL_inst.DYN_IDIV_SEL = "FALSE";
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defparam PLL_inst.DYN_FBDIV_SEL = "FALSE";
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defparam PLL_inst.DYN_MDIV_SEL = "FALSE";
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defparam PLL_inst.DYN_ODIV0_SEL = "FALSE";
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defparam PLL_inst.DYN_ODIV1_SEL = "FALSE";
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defparam PLL_inst.DYN_ODIV2_SEL = "FALSE";
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defparam PLL_inst.DYN_ODIV3_SEL = "FALSE";
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defparam PLL_inst.DYN_ODIV4_SEL = "FALSE";
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defparam PLL_inst.DYN_ODIV5_SEL = "FALSE";
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defparam PLL_inst.DYN_ODIV6_SEL = "FALSE";
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defparam PLL_inst.DYN_DT0_SEL = "FALSE";
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defparam PLL_inst.DYN_DT1_SEL = "FALSE";
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defparam PLL_inst.DYN_DT2_SEL = "FALSE";
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defparam PLL_inst.DYN_DT3_SEL = "FALSE";
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defparam PLL_inst.DYN_ICP_SEL = "TRUE";
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defparam PLL_inst.DYN_LPF_SEL = "TRUE";
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endmodule //Gowin_PLL_MOD
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`timescale 1ns/1ns
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module PLL_INIT
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#(
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parameter CLK_PERIOD = 50,
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parameter MULTI_FAC = 30
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)
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(
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input CLKIN,
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input I_RST,
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input PLLLOCK,
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output O_RST,
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output [5:0] ICPSEL,
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output [2:0] LPFRES,
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output O_LOCK
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);
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localparam WAIT_TIME = 'd2000_000;
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localparam WAIT_CNT = (WAIT_TIME + CLK_PERIOD - 1) / CLK_PERIOD;
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localparam WAIT_WIDTH = $clog2(WAIT_CNT + 1);
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reg [WAIT_WIDTH-1:0] waitcnt = 'd0;
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reg [3:0] RomAddr = 'd0;
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reg [15:0] Rom [15:0];
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reg [15:0] RomDreg ='d0;
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wire [5:0] Regicp = RomDreg[5:0];
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wire [2:0] Regres = RomDreg[10:8];
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reg Waitlock = 'd0;
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reg [7:0] locksig = 8'b0000_0000;
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reg laststep = 1'b0;
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wire validsig = RomDreg[12];
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reg [1:0]enable_r = 2'b00;
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wire Enable = enable_r[1];
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always @(posedge CLKIN or posedge I_RST)
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begin
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if (I_RST)
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enable_r <= 2'b00;
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else
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begin
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enable_r <= {enable_r[0], 1'b1};
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end
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end
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always @(posedge CLKIN or negedge Enable)
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begin
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if (Enable == 1'b0)
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begin
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RomDreg <= 16'h0000;
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Rom[00] <= 16'h1400; //1
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Rom[01] <= (MULTI_FAC > 34) ? 16'h1401
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: (MULTI_FAC > 16) ? 16'h1400
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: 16'h1400; //2
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Rom[02] <= (MULTI_FAC > 34) ? 16'h1501
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: (MULTI_FAC > 16) ? 16'h1500
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: 16'h1500; //3
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Rom[03] <= (MULTI_FAC > 34) ? 16'h1503
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: (MULTI_FAC > 16) ? 16'h1501
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: 16'h1500; //4
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Rom[04] <= (MULTI_FAC > 34) ? 16'h1507
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: (MULTI_FAC > 16) ? 16'h1503
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: 16'h1501; //5
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Rom[05] <= (MULTI_FAC > 34) ? 16'h0605
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: (MULTI_FAC > 16) ? 16'h0602
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: 16'h0601; //6
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Rom[06] <= 16'h0000; //over
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Rom[07] <= (MULTI_FAC > 34) ? 16'h1402
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: (MULTI_FAC > 16) ? 16'h1401
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: 16'h1400; //2.5
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Rom[08] <= (MULTI_FAC > 34) ? 16'h1502
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: (MULTI_FAC > 16) ? 16'h1501
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: 16'h1500; //3.5
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Rom[09] <= (MULTI_FAC > 34) ? 16'h1504
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: (MULTI_FAC > 16) ? 16'h1502
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: 16'h1501; //4.5
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Rom[10] <= (MULTI_FAC > 34) ? 16'h1603
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: (MULTI_FAC > 16) ? 16'h1601
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: 16'h1600; //5.5
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Rom[11] <= 16'h1400; //1.5
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Rom[12] <= 16'h0000;
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Rom[13] <= 16'h0000;
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Rom[14] <= 16'h0000;
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Rom[15] <= 16'h0000;
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end
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else
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RomDreg <= Rom[RomAddr[3:0]];
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end
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reg [3:0]RomAddrVld = 'd0;
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always @ (*) begin
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casex (locksig[5:0])
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6'b111_111 : RomAddrVld = 4'd8;
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6'b011_111 : RomAddrVld = 4'd8;
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6'b111_110 : RomAddrVld = 4'd8;
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6'b111_10x : RomAddrVld = 4'd9;
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6'bx01_111 : RomAddrVld = 4'd7;
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6'b011_110 : RomAddrVld = 4'd8;
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6'bxx0_111 : RomAddrVld = 4'd1;
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6'bx01_110 : RomAddrVld = 4'd2;
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6'b011_10x : RomAddrVld = 4'd3;
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6'b111_0xx : RomAddrVld = 4'd4;
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6'bxxx_011 : RomAddrVld = 4'd1;
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6'bxx0_110 : RomAddrVld = 4'd7;
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6'bx01_100 : RomAddrVld = 4'd8;
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6'b011_000 : RomAddrVld = 4'd9;
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6'b110_000 : RomAddrVld = 4'd10;
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6'bxxx_x01 : RomAddrVld = 4'd0;
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6'bxxx_010 : RomAddrVld = 4'd1;
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6'bxx0_100 : RomAddrVld = 4'd2;
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6'bx01_000 : RomAddrVld = 4'd3;
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6'b010_000 : RomAddrVld = 4'd4;
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6'b100_000 : RomAddrVld = 4'd5;
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6'b000_000 : RomAddrVld = 4'd8;
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default : RomAddrVld = 4'd8;
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endcase
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end
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reg [3:0]state='d0;
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localparam IDLE = 4'd0;
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localparam STATE1 = 4'd1;
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localparam STATE2 = 4'd2;
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localparam STATE3 = 4'd3;
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localparam STATE4 = 4'd4;
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localparam STATE5 = 4'd5;
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localparam STATE6 = 4'd6;
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localparam STATE7 = 4'd7;
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always @(posedge CLKIN or negedge Enable)
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begin
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if (Enable == 1'b0)
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begin
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state <= IDLE;
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RomAddr<=4'b0000;
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laststep <= 1'b0;
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end
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else
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begin
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case (state)
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IDLE:
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begin
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state<=STATE1;
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end
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STATE1:
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begin
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state<=STATE2;
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end
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STATE2:
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begin
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if (laststep==1'b1)
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state<=STATE7;
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else
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state<=STATE3;
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end
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||||
STATE3:
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begin
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if (Waitlock==1'b1)
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state<=STATE4;
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else
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state<= STATE3;
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end
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STATE4:
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begin
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state<=STATE5;
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end
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STATE5:
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begin
|
||||
if (validsig==1'b1)
|
||||
begin
|
||||
RomAddr <= RomAddr + 1;
|
||||
state <= STATE1;
|
||||
end
|
||||
else if (validsig==1'b0 && laststep==1'b0)
|
||||
state <= STATE6;
|
||||
end
|
||||
STATE6:
|
||||
begin
|
||||
RomAddr <= RomAddrVld;
|
||||
laststep <= 1'b1;
|
||||
state <= STATE1;
|
||||
end
|
||||
STATE7:
|
||||
begin
|
||||
state<=STATE7;
|
||||
end
|
||||
|
||||
default: state<=IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLKIN)
|
||||
begin
|
||||
|
||||
|
||||
Waitlock <= (&waitcnt == 1'b1) ? 1'b1 : 1'b0;
|
||||
|
||||
waitcnt <= (state==STATE3) ? (waitcnt+1) : 'd0;
|
||||
|
||||
if (~Enable) locksig <= 8'b0000_0000;
|
||||
else if (state==STATE4) locksig[RomAddr[3:0]] <= PLLLOCK;
|
||||
|
||||
|
||||
end
|
||||
|
||||
assign ICPSEL = Regicp;
|
||||
assign LPFRES = Regres;
|
||||
assign O_RST = (~Enable) || (state==STATE2) ? 1'b1 : 1'b0;
|
||||
assign O_LOCK = (state==STATE7) ? PLLLOCK : 1'b0;
|
||||
|
||||
endmodule
|
||||
260
RTL/spade.sv
260
RTL/spade.sv
@ -13,12 +13,12 @@
|
||||
`endif
|
||||
|
||||
|
||||
module \std::cdc::sync2[1523] (
|
||||
module \std::cdc::sync2[1531] (
|
||||
input clk_i,
|
||||
input input_i,
|
||||
output output__
|
||||
);
|
||||
`COCOTB_CODE( std::cdc::sync2[1523] )
|
||||
`COCOTB_CODE( std::cdc::sync2[1531] )
|
||||
logic \clk ;
|
||||
assign \clk = clk_i;
|
||||
logic \input ;
|
||||
@ -51,7 +51,7 @@ module \std::cdc::sync2_bool (
|
||||
logic _e_544;
|
||||
(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *)
|
||||
|
||||
\std::cdc::sync2[1523] \sync2_0 (.clk_i(\clk ), .input_i(\input ), .output__(_e_544));
|
||||
\std::cdc::sync2[1531] \sync2_0 (.clk_i(\clk ), .input_i(\input ), .output__(_e_544));
|
||||
assign output__ = _e_544;
|
||||
endmodule
|
||||
|
||||
@ -85,29 +85,29 @@ module \std::io::rising_edge (
|
||||
(* src = "<compiler dir>/stdlib/io.spade:12,14" *)
|
||||
reg \old_value ;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *)
|
||||
logic _e_2136;
|
||||
logic _e_2202;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2135;
|
||||
logic _e_2201;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_1034;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,29" *)
|
||||
logic _e_2144;
|
||||
logic _e_2210;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,37" *)
|
||||
logic _e_2145;
|
||||
logic _e_2211;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,9" *)
|
||||
logic _e_2143;
|
||||
logic _e_2209;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,9" *)
|
||||
logic _e_1032;
|
||||
always @(posedge \clk ) begin
|
||||
\old_value <= \value ;
|
||||
end
|
||||
assign _e_2136 = {\old_value };
|
||||
assign _e_2135 = ~_e_2136;
|
||||
assign _e_1034 = _e_2135;
|
||||
assign _e_2144 = {\value };
|
||||
assign _e_2145 = {_e_1034};
|
||||
assign _e_2143 = _e_2144 & _e_2145;
|
||||
assign _e_1032 = _e_2143;
|
||||
assign _e_2202 = {\old_value };
|
||||
assign _e_2201 = ~_e_2202;
|
||||
assign _e_1034 = _e_2201;
|
||||
assign _e_2210 = {\value };
|
||||
assign _e_2211 = {_e_1034};
|
||||
assign _e_2209 = _e_2210 & _e_2211;
|
||||
assign _e_1032 = _e_2209;
|
||||
assign output__ = _e_1032;
|
||||
endmodule
|
||||
|
||||
@ -125,64 +125,173 @@ module \std::io::falling_edge (
|
||||
(* src = "<compiler dir>/stdlib/io.spade:27,14" *)
|
||||
reg \old_value ;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *)
|
||||
logic _e_2154;
|
||||
logic _e_2220;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2153;
|
||||
logic _e_2219;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_1041;
|
||||
logic _e_2218;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,29" *)
|
||||
logic _e_2162;
|
||||
logic _e_2228;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,37" *)
|
||||
logic _e_2163;
|
||||
logic _e_2229;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,9" *)
|
||||
logic _e_2161;
|
||||
logic _e_2227;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,9" *)
|
||||
logic _e_2160;
|
||||
logic _e_2226;
|
||||
always @(posedge \clk ) begin
|
||||
\old_value <= \value ;
|
||||
end
|
||||
assign _e_2154 = {\value };
|
||||
assign _e_2153 = ~_e_2154;
|
||||
assign _e_1041 = _e_2153;
|
||||
assign _e_2162 = {_e_1041};
|
||||
assign _e_2163 = {\old_value };
|
||||
assign _e_2161 = _e_2162 & _e_2163;
|
||||
assign _e_2160 = _e_2161;
|
||||
assign output__ = _e_2160;
|
||||
assign _e_2220 = {\value };
|
||||
assign _e_2219 = ~_e_2220;
|
||||
assign _e_2218 = _e_2219;
|
||||
assign _e_2228 = {_e_2218};
|
||||
assign _e_2229 = {\old_value };
|
||||
assign _e_2227 = _e_2228 & _e_2229;
|
||||
assign _e_2226 = _e_2227;
|
||||
assign output__ = _e_2226;
|
||||
endmodule
|
||||
|
||||
|
||||
module main (
|
||||
input clk,
|
||||
output[3:0] leds
|
||||
output[3:0] leds,
|
||||
output tmds_clk,
|
||||
output[2:0] tmds
|
||||
);
|
||||
`COCOTB_CODE( main )
|
||||
logic[3:0] \leds_mut ;
|
||||
assign leds = \leds_mut ;
|
||||
localparam[23:0] _e_1734 = 1;
|
||||
(* src = "src/main.spade:4,34" *)
|
||||
logic[23:0] _e_1732;
|
||||
(* src = "src/main.spade:4,14" *)
|
||||
reg[23:0] \counter ;
|
||||
localparam[23:0] _e_1740 = 20;
|
||||
(* src = "src/main.spade:6,16" *)
|
||||
logic[23:0] _e_1738;
|
||||
(* src = "src/main.spade:6,16" *)
|
||||
logic[23:0] _e_1737;
|
||||
(* src = "src/main.spade:6,16" *)
|
||||
logic[3:0] _e_1736;
|
||||
(* src = "src/main.spade:4,34" *)
|
||||
logic \tmds_clk_mut ;
|
||||
assign tmds_clk = \tmds_clk_mut ;
|
||||
logic[2:0] \tmds_mut ;
|
||||
assign tmds = \tmds_mut ;
|
||||
(* src = "src/main.spade:9,35" *)
|
||||
logic _e_2156;
|
||||
(* src = "src/main.spade:9,35" *)
|
||||
logic _e_2157_mut;
|
||||
(* src = "src/main.spade:9,35" *)
|
||||
logic _e_1733;
|
||||
(* src = "src/main.spade:9,35" *)
|
||||
logic _e_1733_mut;
|
||||
(* src = "src/main.spade:9,9" *)
|
||||
logic \clk_pll ;
|
||||
(* src = "src/main.spade:9,9" *)
|
||||
logic \clk_pll_wire_mut ;
|
||||
(* src = "src/main.spade:10,37" *)
|
||||
logic _e_2158;
|
||||
(* src = "src/main.spade:10,37" *)
|
||||
logic _e_2159_mut;
|
||||
(* src = "src/main.spade:10,37" *)
|
||||
logic _e_1737;
|
||||
(* src = "src/main.spade:10,37" *)
|
||||
logic _e_1737_mut;
|
||||
(* src = "src/main.spade:10,9" *)
|
||||
logic \lock_pll ;
|
||||
(* src = "src/main.spade:10,9" *)
|
||||
logic \lock_pll_wire_mut ;
|
||||
localparam[31:0] _e_1748 = 32'd50000000;
|
||||
(* src = "<compiler dir>/core/ops.spade:53,9" *)
|
||||
logic _e_1746;
|
||||
localparam[31:0] _e_1750 = 32'd0;
|
||||
localparam[31:0] _e_1754 = 32'd1;
|
||||
(* src = "src/main.spade:13,75" *)
|
||||
logic[31:0] _e_1752;
|
||||
(* src = "src/main.spade:13,38" *)
|
||||
logic[31:0] _e_1745;
|
||||
(* src = "src/main.spade:13,18" *)
|
||||
reg[31:0] \counter ;
|
||||
localparam[31:0] _e_1760 = 32'd0;
|
||||
(* src = "<compiler dir>/core/ops.spade:53,9" *)
|
||||
logic _e_1758;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *)
|
||||
logic _e_2242;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2241;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_1762;
|
||||
(* src = "src/main.spade:14,29" *)
|
||||
logic _e_1757;
|
||||
(* src = "src/main.spade:14,18" *)
|
||||
reg \on ;
|
||||
localparam[0:0] _e_1770 = 0;
|
||||
localparam[0:0] _e_1771 = 0;
|
||||
localparam[0:0] _e_1772 = 0;
|
||||
(* src = "src/main.spade:19,16" *)
|
||||
logic[2:0] _e_1769;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *)
|
||||
logic _e_2250;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2249;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2248;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *)
|
||||
logic _e_2258;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2257;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_1777;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *)
|
||||
logic _e_2266;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2265;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2264;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *)
|
||||
logic _e_2274;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_2273;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *)
|
||||
logic _e_1781;
|
||||
(* src = "src/main.spade:21,16" *)
|
||||
logic[3:0] _e_1774;
|
||||
|
||||
\core::ops::impl#77::wrapping_add[1524] \wrapping_add_0 (.self_i(\counter ), .rhs_i(_e_1734), .output__(_e_1732));
|
||||
always @(posedge \clk ) begin
|
||||
\counter <= _e_1732;
|
||||
assign _e_2156 = _e_2157_mut;
|
||||
assign _e_1733 = {_e_2156};
|
||||
assign {_e_2157_mut} = _e_1733_mut;
|
||||
assign \clk_pll = _e_1733;
|
||||
assign _e_1733_mut = \clk_pll_wire_mut ;
|
||||
|
||||
assign _e_2158 = _e_2159_mut;
|
||||
assign _e_1737 = {_e_2158};
|
||||
assign {_e_2159_mut} = _e_1737_mut;
|
||||
assign \lock_pll = _e_1737;
|
||||
assign _e_1737_mut = \lock_pll_wire_mut ;
|
||||
(* src = "src/main.spade:11,5" *)
|
||||
|
||||
pll \pll_0 (.clkin(\clk ), .init_clk(\clk ), .clkout0(\clk_pll_wire_mut ), .lock(\lock_pll_wire_mut ));
|
||||
assign _e_1746 = \counter == _e_1748;
|
||||
(* src = "src/main.spade:13,75" *)
|
||||
|
||||
\core::ops::impl#77::wrapping_add[1533] \wrapping_add_0 (.self_i(\counter ), .rhs_i(_e_1754), .output__(_e_1752));
|
||||
assign _e_1745 = _e_1746 ? _e_1750 : _e_1752;
|
||||
always @(posedge \clk_pll ) begin
|
||||
\counter <= _e_1745;
|
||||
end
|
||||
assign _e_1738 = \counter >> _e_1740;
|
||||
(* src = "src/main.spade:6,16" *)
|
||||
|
||||
\std::conv::impl#14::as_bits[1525] \as_bits_0 (.self_i(_e_1738), .output__(_e_1737));
|
||||
assign _e_1736 = _e_1737[3-:4];
|
||||
assign \leds_mut = _e_1736;
|
||||
assign _e_1758 = \counter == _e_1760;
|
||||
assign _e_2242 = {\on };
|
||||
assign _e_2241 = ~_e_2242;
|
||||
assign _e_1762 = _e_2241;
|
||||
assign _e_1757 = _e_1758 ? _e_1762 : \on ;
|
||||
always @(posedge \clk_pll ) begin
|
||||
\on <= _e_1757;
|
||||
end
|
||||
assign \tmds_clk_mut = \clk_pll ;
|
||||
assign _e_1769 = {_e_1772, _e_1771, _e_1770};
|
||||
assign \tmds_mut = _e_1769;
|
||||
assign _e_2250 = {\on };
|
||||
assign _e_2249 = ~_e_2250;
|
||||
assign _e_2248 = _e_2249;
|
||||
assign _e_2258 = {\on };
|
||||
assign _e_2257 = ~_e_2258;
|
||||
assign _e_1777 = _e_2257;
|
||||
assign _e_2266 = {\on };
|
||||
assign _e_2265 = ~_e_2266;
|
||||
assign _e_2264 = _e_2265;
|
||||
assign _e_2274 = {\lock_pll };
|
||||
assign _e_2273 = ~_e_2274;
|
||||
assign _e_1781 = _e_2273;
|
||||
assign _e_1774 = {_e_1781, _e_2264, _e_1777, _e_2248};
|
||||
assign \leds_mut = _e_1774;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -239,19 +348,6 @@ module \std::conv::impl#12::as_bool (
|
||||
endmodule
|
||||
|
||||
|
||||
module \std::conv::impl#14::as_bits[1525] (
|
||||
input[23:0] self_i,
|
||||
output[23:0] output__
|
||||
);
|
||||
`COCOTB_CODE( std::conv::impl#14::as_bits[1525] )
|
||||
logic[23:0] \self ;
|
||||
assign \self = self_i;
|
||||
logic[23:0] _e_917;
|
||||
assign _e_917 = \self ;
|
||||
assign output__ = _e_917;
|
||||
endmodule
|
||||
|
||||
|
||||
module \std::default::impl#17::hacky_default (
|
||||
input self_i,
|
||||
output output__
|
||||
@ -272,27 +368,27 @@ module \std::default::impl#18::hacky_default (
|
||||
endmodule
|
||||
|
||||
|
||||
module \core::ops::impl#77::wrapping_add[1524] (
|
||||
input[23:0] self_i,
|
||||
input[23:0] rhs_i,
|
||||
output[23:0] output__
|
||||
module \core::ops::impl#77::wrapping_add[1533] (
|
||||
input[31:0] self_i,
|
||||
input[31:0] rhs_i,
|
||||
output[31:0] output__
|
||||
);
|
||||
`COCOTB_CODE( core::ops::impl#77::wrapping_add[1524] )
|
||||
logic[23:0] \self ;
|
||||
`COCOTB_CODE( core::ops::impl#77::wrapping_add[1533] )
|
||||
logic[31:0] \self ;
|
||||
assign \self = self_i;
|
||||
logic[23:0] \rhs ;
|
||||
logic[31:0] \rhs ;
|
||||
assign \rhs = rhs_i;
|
||||
(* src = "<compiler dir>/core/ops.spade:166,62" *)
|
||||
logic[24:0] _e_1883;
|
||||
logic[24:0] \bits ;
|
||||
logic[32:0] _e_1923;
|
||||
logic[32:0] \bits ;
|
||||
(* src = "<compiler dir>/core/ops.spade:167,34" *)
|
||||
logic[23:0] _e_1888;
|
||||
logic[23:0] _e_1887;
|
||||
assign _e_1883 = \self + \rhs ;
|
||||
assign \bits = _e_1883;
|
||||
assign _e_1888 = \bits [23-:24];
|
||||
assign _e_1887 = _e_1888;
|
||||
assign output__ = _e_1887;
|
||||
logic[31:0] _e_1928;
|
||||
logic[31:0] _e_1927;
|
||||
assign _e_1923 = \self + \rhs ;
|
||||
assign \bits = _e_1923;
|
||||
assign _e_1928 = \bits [31-:32];
|
||||
assign _e_1927 = _e_1928;
|
||||
assign output__ = _e_1927;
|
||||
endmodule
|
||||
|
||||
`default_nettype none
|
||||
306
RTL/spade.v
Normal file
306
RTL/spade.v
Normal file
@ -0,0 +1,306 @@
|
||||
module \std::cdc::sync2[1531] (
|
||||
clk_i,
|
||||
input_i,
|
||||
output__
|
||||
);
|
||||
input clk_i;
|
||||
input input_i;
|
||||
output wire output__;
|
||||
wire \clk ;
|
||||
assign \clk = clk_i;
|
||||
wire \input ;
|
||||
assign \input = input_i;
|
||||
(* src = "<compiler dir>/stdlib/cdc.spade:14,14" *) reg \sync1 ;
|
||||
(* src = "<compiler dir>/stdlib/cdc.spade:15,14" *) reg \sync2 ;
|
||||
always @(posedge \clk ) \sync1 <= \input ;
|
||||
always @(posedge \clk ) \sync2 <= \sync1 ;
|
||||
assign output__ = \sync2 ;
|
||||
endmodule
|
||||
module \std::cdc::sync2_bool (
|
||||
clk_i,
|
||||
input_i,
|
||||
output__
|
||||
);
|
||||
input clk_i;
|
||||
input input_i;
|
||||
output wire output__;
|
||||
wire \clk ;
|
||||
assign \clk = clk_i;
|
||||
wire \input ;
|
||||
assign \input = input_i;
|
||||
(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *) wire _e_544;
|
||||
(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *) \std::cdc::sync2[1531] \sync2_0 (
|
||||
.clk_i(\clk ),
|
||||
.input_i(\input ),
|
||||
.output__(_e_544)
|
||||
);
|
||||
assign output__ = _e_544;
|
||||
endmodule
|
||||
module \std::conv::tri_to_bool (
|
||||
t_i,
|
||||
output__
|
||||
);
|
||||
input t_i;
|
||||
output wire output__;
|
||||
wire \t ;
|
||||
assign \t = t_i;
|
||||
(* src = "<compiler dir>/stdlib/conv.spade:80,5" *) wire _e_828;
|
||||
(* src = "<compiler dir>/stdlib/conv.spade:80,5" *) \std::conv::impl#12::as_bool \as_bool_0 (
|
||||
.self_i(\t ),
|
||||
.output__(_e_828)
|
||||
);
|
||||
assign output__ = _e_828;
|
||||
endmodule
|
||||
module \std::io::rising_edge (
|
||||
clk_i,
|
||||
value_i,
|
||||
output__
|
||||
);
|
||||
input clk_i;
|
||||
input value_i;
|
||||
output wire output__;
|
||||
wire \clk ;
|
||||
assign \clk = clk_i;
|
||||
wire \value ;
|
||||
assign \value = value_i;
|
||||
(* src = "<compiler dir>/stdlib/io.spade:12,14" *) reg \old_value ;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2202;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2201;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1034;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,29" *) wire _e_2210;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,37" *) wire _e_2211;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2209;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_1032;
|
||||
always @(posedge \clk ) \old_value <= \value ;
|
||||
assign _e_2202 = {\old_value };
|
||||
assign _e_2201 = ~_e_2202;
|
||||
assign _e_1034 = _e_2201;
|
||||
assign _e_2210 = {\value };
|
||||
assign _e_2211 = {_e_1034};
|
||||
assign _e_2209 = _e_2210 & _e_2211;
|
||||
assign _e_1032 = _e_2209;
|
||||
assign output__ = _e_1032;
|
||||
endmodule
|
||||
module \std::io::falling_edge (
|
||||
clk_i,
|
||||
value_i,
|
||||
output__
|
||||
);
|
||||
input clk_i;
|
||||
input value_i;
|
||||
output wire output__;
|
||||
wire \clk ;
|
||||
assign \clk = clk_i;
|
||||
wire \value ;
|
||||
assign \value = value_i;
|
||||
(* src = "<compiler dir>/stdlib/io.spade:27,14" *) reg \old_value ;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2220;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2219;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2218;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,29" *) wire _e_2228;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,37" *) wire _e_2229;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2227;
|
||||
(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2226;
|
||||
always @(posedge \clk ) \old_value <= \value ;
|
||||
assign _e_2220 = {\value };
|
||||
assign _e_2219 = ~_e_2220;
|
||||
assign _e_2218 = _e_2219;
|
||||
assign _e_2228 = {_e_2218};
|
||||
assign _e_2229 = {\old_value };
|
||||
assign _e_2227 = _e_2228 & _e_2229;
|
||||
assign _e_2226 = _e_2227;
|
||||
assign output__ = _e_2226;
|
||||
endmodule
|
||||
module main (
|
||||
clk,
|
||||
leds,
|
||||
tmds_clk,
|
||||
tmds
|
||||
);
|
||||
input clk;
|
||||
output wire [3:0] leds;
|
||||
output wire tmds_clk;
|
||||
output wire [2:0] tmds;
|
||||
wire [3:0] \leds_mut ;
|
||||
assign leds = \leds_mut ;
|
||||
wire \tmds_clk_mut ;
|
||||
assign tmds_clk = \tmds_clk_mut ;
|
||||
wire [2:0] \tmds_mut ;
|
||||
assign tmds = \tmds_mut ;
|
||||
(* src = "src/main.spade:9,35" *) wire _e_2156;
|
||||
(* src = "src/main.spade:9,35" *) wire _e_2157_mut;
|
||||
(* src = "src/main.spade:9,35" *) wire _e_1733;
|
||||
(* src = "src/main.spade:9,35" *) wire _e_1733_mut;
|
||||
(* src = "src/main.spade:9,9" *) wire \clk_pll ;
|
||||
(* src = "src/main.spade:9,9" *) wire \clk_pll_wire_mut ;
|
||||
(* src = "src/main.spade:10,37" *) wire _e_2158;
|
||||
(* src = "src/main.spade:10,37" *) wire _e_2159_mut;
|
||||
(* src = "src/main.spade:10,37" *) wire _e_1737;
|
||||
(* src = "src/main.spade:10,37" *) wire _e_1737_mut;
|
||||
(* src = "src/main.spade:10,9" *) wire \lock_pll ;
|
||||
(* src = "src/main.spade:10,9" *) wire \lock_pll_wire_mut ;
|
||||
localparam [31:0] _e_1748 = 32'd50000000;
|
||||
(* src = "<compiler dir>/core/ops.spade:53,9" *) wire _e_1746;
|
||||
localparam [31:0] _e_1750 = 32'd0;
|
||||
localparam [31:0] _e_1754 = 32'd1;
|
||||
(* src = "src/main.spade:13,75" *) wire [31:0] _e_1752;
|
||||
(* src = "src/main.spade:13,38" *) wire [31:0] _e_1745;
|
||||
(* src = "src/main.spade:13,18" *) reg [31:0] \counter ;
|
||||
localparam [31:0] _e_1760 = 32'd0;
|
||||
(* src = "<compiler dir>/core/ops.spade:53,9" *) wire _e_1758;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2242;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2241;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1762;
|
||||
(* src = "src/main.spade:14,29" *) wire _e_1757;
|
||||
(* src = "src/main.spade:14,18" *) reg \on ;
|
||||
localparam [0:0] _e_1770 = 0;
|
||||
localparam [0:0] _e_1771 = 0;
|
||||
localparam [0:0] _e_1772 = 0;
|
||||
(* src = "src/main.spade:19,16" *) wire [2:0] _e_1769;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2250;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2249;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2248;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2258;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2257;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1777;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2266;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2265;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2264;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2274;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2273;
|
||||
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1781;
|
||||
(* src = "src/main.spade:21,16" *) wire [3:0] _e_1774;
|
||||
assign _e_2156 = _e_2157_mut;
|
||||
assign _e_1733 = {_e_2156};
|
||||
assign {_e_2157_mut} = _e_1733_mut;
|
||||
assign \clk_pll = _e_1733;
|
||||
assign _e_1733_mut = \clk_pll_wire_mut ;
|
||||
assign _e_2158 = _e_2159_mut;
|
||||
assign _e_1737 = {_e_2158};
|
||||
assign {_e_2159_mut} = _e_1737_mut;
|
||||
assign \lock_pll = _e_1737;
|
||||
assign _e_1737_mut = \lock_pll_wire_mut ;
|
||||
wire \clk ;
|
||||
(* src = "src/main.spade:11,5" *) pll \pll_0 (
|
||||
.clkin(\clk ),
|
||||
.init_clk(\clk ),
|
||||
.clkout0(\clk_pll_wire_mut ),
|
||||
.lock(\lock_pll_wire_mut )
|
||||
);
|
||||
assign _e_1746 = \counter == _e_1748;
|
||||
(* src = "src/main.spade:13,75" *) \core::ops::impl#77::wrapping_add[1533] \wrapping_add_0 (
|
||||
.self_i(\counter ),
|
||||
.rhs_i(_e_1754),
|
||||
.output__(_e_1752)
|
||||
);
|
||||
assign _e_1745 = (_e_1746 ? _e_1750 : _e_1752);
|
||||
always @(posedge \clk_pll ) \counter <= _e_1745;
|
||||
assign _e_1758 = \counter == _e_1760;
|
||||
assign _e_2242 = {\on };
|
||||
assign _e_2241 = ~_e_2242;
|
||||
assign _e_1762 = _e_2241;
|
||||
assign _e_1757 = (_e_1758 ? _e_1762 : \on );
|
||||
always @(posedge \clk_pll ) \on <= _e_1757;
|
||||
assign \tmds_clk_mut = \clk_pll ;
|
||||
assign _e_1769 = {_e_1772, _e_1771, _e_1770};
|
||||
assign \tmds_mut = _e_1769;
|
||||
assign _e_2250 = {\on };
|
||||
assign _e_2249 = ~_e_2250;
|
||||
assign _e_2248 = _e_2249;
|
||||
assign _e_2258 = {\on };
|
||||
assign _e_2257 = ~_e_2258;
|
||||
assign _e_1777 = _e_2257;
|
||||
assign _e_2266 = {\on };
|
||||
assign _e_2265 = ~_e_2266;
|
||||
assign _e_2264 = _e_2265;
|
||||
assign _e_2274 = {\lock_pll };
|
||||
assign _e_2273 = ~_e_2274;
|
||||
assign _e_1781 = _e_2273;
|
||||
assign _e_1774 = {_e_1781, _e_2264, _e_1777, _e_2248};
|
||||
assign \leds_mut = _e_1774;
|
||||
endmodule
|
||||
module \std::conv::impl#10::as_clock (
|
||||
self_i,
|
||||
output__
|
||||
);
|
||||
input self_i;
|
||||
output wire output__;
|
||||
wire \self ;
|
||||
assign \self = self_i;
|
||||
wire _e_872;
|
||||
assign _e_872 = \self ;
|
||||
assign output__ = _e_872;
|
||||
endmodule
|
||||
module \std::conv::impl#10::as_uint (
|
||||
self_i,
|
||||
output__
|
||||
);
|
||||
input self_i;
|
||||
output wire output__;
|
||||
wire \self ;
|
||||
assign \self = self_i;
|
||||
wire _e_876;
|
||||
assign _e_876 = \self ;
|
||||
assign output__ = _e_876;
|
||||
endmodule
|
||||
module \std::conv::impl#11::as_bool (
|
||||
self_i,
|
||||
output__
|
||||
);
|
||||
input self_i;
|
||||
output wire output__;
|
||||
wire \self ;
|
||||
assign \self = self_i;
|
||||
wire _e_887;
|
||||
assign _e_887 = \self ;
|
||||
assign output__ = _e_887;
|
||||
endmodule
|
||||
module \std::conv::impl#12::as_bool (
|
||||
self_i,
|
||||
output__
|
||||
);
|
||||
input self_i;
|
||||
output wire output__;
|
||||
wire \self ;
|
||||
assign \self = self_i;
|
||||
wire _e_895;
|
||||
assign _e_895 = \self ;
|
||||
assign output__ = _e_895;
|
||||
endmodule
|
||||
module \std::default::impl#17::hacky_default (
|
||||
self_i,
|
||||
output__
|
||||
);
|
||||
input self_i;
|
||||
output wire output__;
|
||||
wire \self ;
|
||||
assign \self = self_i;
|
||||
localparam [0:0] _e_971 = 0;
|
||||
assign output__ = _e_971;
|
||||
endmodule
|
||||
module \std::default::impl#18::hacky_default ;
|
||||
|
||||
endmodule
|
||||
module \core::ops::impl#77::wrapping_add[1533] (
|
||||
self_i,
|
||||
rhs_i,
|
||||
output__
|
||||
);
|
||||
input [31:0] self_i;
|
||||
input [31:0] rhs_i;
|
||||
output wire [31:0] output__;
|
||||
wire [31:0] \self ;
|
||||
assign \self = self_i;
|
||||
wire [31:0] \rhs ;
|
||||
assign \rhs = rhs_i;
|
||||
(* src = "<compiler dir>/core/ops.spade:166,62" *) wire [32:0] _e_1923;
|
||||
wire [32:0] \bits ;
|
||||
(* src = "<compiler dir>/core/ops.spade:167,34" *) wire [31:0] _e_1928;
|
||||
wire [31:0] _e_1927;
|
||||
assign _e_1923 = \self + \rhs ;
|
||||
assign \bits = _e_1923;
|
||||
assign _e_1928 = \bits [31-:32];
|
||||
assign _e_1927 = _e_1928;
|
||||
assign output__ = _e_1927;
|
||||
endmodule
|
||||
`default_nettype none
|
||||
Reference in New Issue
Block a user