307 lines
9.0 KiB
Verilog
307 lines
9.0 KiB
Verilog
module \std::cdc::sync2[1531] (
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clk_i,
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input_i,
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output__
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);
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input clk_i;
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input input_i;
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output wire output__;
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wire \clk ;
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assign \clk = clk_i;
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wire \input ;
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assign \input = input_i;
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(* src = "<compiler dir>/stdlib/cdc.spade:14,14" *) reg \sync1 ;
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(* src = "<compiler dir>/stdlib/cdc.spade:15,14" *) reg \sync2 ;
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always @(posedge \clk ) \sync1 <= \input ;
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always @(posedge \clk ) \sync2 <= \sync1 ;
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assign output__ = \sync2 ;
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endmodule
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module \std::cdc::sync2_bool (
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clk_i,
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input_i,
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output__
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);
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input clk_i;
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input input_i;
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output wire output__;
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wire \clk ;
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assign \clk = clk_i;
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wire \input ;
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assign \input = input_i;
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(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *) wire _e_544;
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(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *) \std::cdc::sync2[1531] \sync2_0 (
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.clk_i(\clk ),
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.input_i(\input ),
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.output__(_e_544)
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);
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assign output__ = _e_544;
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endmodule
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module \std::conv::tri_to_bool (
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t_i,
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output__
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);
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input t_i;
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output wire output__;
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wire \t ;
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assign \t = t_i;
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(* src = "<compiler dir>/stdlib/conv.spade:80,5" *) wire _e_828;
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(* src = "<compiler dir>/stdlib/conv.spade:80,5" *) \std::conv::impl#12::as_bool \as_bool_0 (
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.self_i(\t ),
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.output__(_e_828)
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);
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assign output__ = _e_828;
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endmodule
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module \std::io::rising_edge (
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clk_i,
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value_i,
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output__
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);
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input clk_i;
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input value_i;
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output wire output__;
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wire \clk ;
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assign \clk = clk_i;
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wire \value ;
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assign \value = value_i;
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(* src = "<compiler dir>/stdlib/io.spade:12,14" *) reg \old_value ;
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(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2202;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2201;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1034;
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(* src = "<compiler dir>/core/ops.spade:297,29" *) wire _e_2210;
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(* src = "<compiler dir>/core/ops.spade:297,37" *) wire _e_2211;
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(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2209;
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(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_1032;
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always @(posedge \clk ) \old_value <= \value ;
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assign _e_2202 = {\old_value };
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assign _e_2201 = ~_e_2202;
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assign _e_1034 = _e_2201;
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assign _e_2210 = {\value };
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assign _e_2211 = {_e_1034};
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assign _e_2209 = _e_2210 & _e_2211;
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assign _e_1032 = _e_2209;
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assign output__ = _e_1032;
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endmodule
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module \std::io::falling_edge (
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clk_i,
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value_i,
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output__
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);
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input clk_i;
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input value_i;
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output wire output__;
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wire \clk ;
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assign \clk = clk_i;
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wire \value ;
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assign \value = value_i;
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(* src = "<compiler dir>/stdlib/io.spade:27,14" *) reg \old_value ;
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(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2220;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2219;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2218;
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(* src = "<compiler dir>/core/ops.spade:297,29" *) wire _e_2228;
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(* src = "<compiler dir>/core/ops.spade:297,37" *) wire _e_2229;
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(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2227;
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(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2226;
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always @(posedge \clk ) \old_value <= \value ;
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assign _e_2220 = {\value };
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assign _e_2219 = ~_e_2220;
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assign _e_2218 = _e_2219;
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assign _e_2228 = {_e_2218};
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assign _e_2229 = {\old_value };
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assign _e_2227 = _e_2228 & _e_2229;
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assign _e_2226 = _e_2227;
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assign output__ = _e_2226;
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endmodule
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module main (
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clk,
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leds,
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tmds_clk,
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tmds
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);
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input clk;
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output wire [3:0] leds;
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output wire tmds_clk;
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output wire [2:0] tmds;
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wire [3:0] \leds_mut ;
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assign leds = \leds_mut ;
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wire \tmds_clk_mut ;
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assign tmds_clk = \tmds_clk_mut ;
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wire [2:0] \tmds_mut ;
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assign tmds = \tmds_mut ;
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(* src = "src/main.spade:9,35" *) wire _e_2156;
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(* src = "src/main.spade:9,35" *) wire _e_2157_mut;
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(* src = "src/main.spade:9,35" *) wire _e_1733;
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(* src = "src/main.spade:9,35" *) wire _e_1733_mut;
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(* src = "src/main.spade:9,9" *) wire \clk_pll ;
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(* src = "src/main.spade:9,9" *) wire \clk_pll_wire_mut ;
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(* src = "src/main.spade:10,37" *) wire _e_2158;
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(* src = "src/main.spade:10,37" *) wire _e_2159_mut;
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(* src = "src/main.spade:10,37" *) wire _e_1737;
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(* src = "src/main.spade:10,37" *) wire _e_1737_mut;
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(* src = "src/main.spade:10,9" *) wire \lock_pll ;
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(* src = "src/main.spade:10,9" *) wire \lock_pll_wire_mut ;
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localparam [31:0] _e_1748 = 32'd50000000;
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(* src = "<compiler dir>/core/ops.spade:53,9" *) wire _e_1746;
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localparam [31:0] _e_1750 = 32'd0;
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localparam [31:0] _e_1754 = 32'd1;
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(* src = "src/main.spade:13,75" *) wire [31:0] _e_1752;
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(* src = "src/main.spade:13,38" *) wire [31:0] _e_1745;
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(* src = "src/main.spade:13,18" *) reg [31:0] \counter ;
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localparam [31:0] _e_1760 = 32'd0;
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(* src = "<compiler dir>/core/ops.spade:53,9" *) wire _e_1758;
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(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2242;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2241;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1762;
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(* src = "src/main.spade:14,29" *) wire _e_1757;
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(* src = "src/main.spade:14,18" *) reg \on ;
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localparam [0:0] _e_1770 = 0;
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localparam [0:0] _e_1771 = 0;
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localparam [0:0] _e_1772 = 0;
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(* src = "src/main.spade:19,16" *) wire [2:0] _e_1769;
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(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2250;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2249;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2248;
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(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2258;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2257;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1777;
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(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2266;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2265;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2264;
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(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2274;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2273;
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(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1781;
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(* src = "src/main.spade:21,16" *) wire [3:0] _e_1774;
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assign _e_2156 = _e_2157_mut;
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assign _e_1733 = {_e_2156};
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assign {_e_2157_mut} = _e_1733_mut;
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assign \clk_pll = _e_1733;
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assign _e_1733_mut = \clk_pll_wire_mut ;
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assign _e_2158 = _e_2159_mut;
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assign _e_1737 = {_e_2158};
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assign {_e_2159_mut} = _e_1737_mut;
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assign \lock_pll = _e_1737;
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assign _e_1737_mut = \lock_pll_wire_mut ;
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wire \clk ;
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(* src = "src/main.spade:11,5" *) pll \pll_0 (
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.clkin(\clk ),
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.init_clk(\clk ),
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.clkout0(\clk_pll_wire_mut ),
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.lock(\lock_pll_wire_mut )
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);
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assign _e_1746 = \counter == _e_1748;
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(* src = "src/main.spade:13,75" *) \core::ops::impl#77::wrapping_add[1533] \wrapping_add_0 (
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.self_i(\counter ),
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.rhs_i(_e_1754),
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.output__(_e_1752)
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);
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assign _e_1745 = (_e_1746 ? _e_1750 : _e_1752);
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always @(posedge \clk_pll ) \counter <= _e_1745;
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assign _e_1758 = \counter == _e_1760;
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assign _e_2242 = {\on };
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assign _e_2241 = ~_e_2242;
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assign _e_1762 = _e_2241;
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assign _e_1757 = (_e_1758 ? _e_1762 : \on );
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always @(posedge \clk_pll ) \on <= _e_1757;
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assign \tmds_clk_mut = \clk_pll ;
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assign _e_1769 = {_e_1772, _e_1771, _e_1770};
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assign \tmds_mut = _e_1769;
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assign _e_2250 = {\on };
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assign _e_2249 = ~_e_2250;
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assign _e_2248 = _e_2249;
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assign _e_2258 = {\on };
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assign _e_2257 = ~_e_2258;
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assign _e_1777 = _e_2257;
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assign _e_2266 = {\on };
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assign _e_2265 = ~_e_2266;
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assign _e_2264 = _e_2265;
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assign _e_2274 = {\lock_pll };
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assign _e_2273 = ~_e_2274;
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assign _e_1781 = _e_2273;
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assign _e_1774 = {_e_1781, _e_2264, _e_1777, _e_2248};
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assign \leds_mut = _e_1774;
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endmodule
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module \std::conv::impl#10::as_clock (
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self_i,
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output__
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);
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input self_i;
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output wire output__;
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wire \self ;
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assign \self = self_i;
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wire _e_872;
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assign _e_872 = \self ;
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assign output__ = _e_872;
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endmodule
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module \std::conv::impl#10::as_uint (
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self_i,
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output__
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);
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input self_i;
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output wire output__;
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wire \self ;
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assign \self = self_i;
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wire _e_876;
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assign _e_876 = \self ;
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assign output__ = _e_876;
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endmodule
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module \std::conv::impl#11::as_bool (
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self_i,
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output__
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);
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input self_i;
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output wire output__;
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wire \self ;
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assign \self = self_i;
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wire _e_887;
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assign _e_887 = \self ;
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assign output__ = _e_887;
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endmodule
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module \std::conv::impl#12::as_bool (
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self_i,
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output__
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);
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input self_i;
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output wire output__;
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wire \self ;
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assign \self = self_i;
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wire _e_895;
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assign _e_895 = \self ;
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assign output__ = _e_895;
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endmodule
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module \std::default::impl#17::hacky_default (
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self_i,
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output__
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);
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input self_i;
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output wire output__;
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wire \self ;
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assign \self = self_i;
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localparam [0:0] _e_971 = 0;
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assign output__ = _e_971;
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endmodule
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module \std::default::impl#18::hacky_default ;
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endmodule
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module \core::ops::impl#77::wrapping_add[1533] (
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self_i,
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rhs_i,
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output__
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);
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input [31:0] self_i;
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input [31:0] rhs_i;
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output wire [31:0] output__;
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wire [31:0] \self ;
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assign \self = self_i;
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wire [31:0] \rhs ;
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assign \rhs = rhs_i;
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(* src = "<compiler dir>/core/ops.spade:166,62" *) wire [32:0] _e_1923;
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wire [32:0] \bits ;
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(* src = "<compiler dir>/core/ops.spade:167,34" *) wire [31:0] _e_1928;
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wire [31:0] _e_1927;
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assign _e_1923 = \self + \rhs ;
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assign \bits = _e_1923;
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assign _e_1928 = \bits [31-:32];
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assign _e_1927 = _e_1928;
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assign output__ = _e_1927;
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endmodule
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`default_nettype none
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