This commit is contained in:
2026-06-18 23:10:59 +02:00
parent 0d4fd7957f
commit 50dbc682d9
29 changed files with 2007161 additions and 93 deletions

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW5AST-138C" package="PBGA484A" speed="1" partNumber="GW5AST-LV138PG484AC1/I0"/>
<FileList>
<File path="/work/RTL/spade.v" type="verilog"/>
<File path="/work/RTL/pll.v" type="verilog"/>
<File path="/work/RTL/gowin_pll_mod.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="5.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="/work/impl/gwsynthesis/build.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="top_module" value="main"/>
<Option type="vcc" value="0.9"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>