w

Dockerfile

@@ -6,7 +6,7 @@ RUN apt install -y \
     tar
     
 RUN wget "https://cdn.gowinsemi.com.cn/Gowin_V1.9.11.03_Education_Linux.tar.gz" -O gowin.tar.gz
-RUN tar --exclude='Programmer/doc/*' -xvzf gowin.tar.gz
+RUN tar -xvzf gowin.tar.gz
 RUN rm -f IDE/lib/libfreetype.so.6
 RUN rm -f gowin.tar.gz
 
@@ -25,3 +25,22 @@ RUN apt install -y \
     libasound2 \
     libgssapi-krb5-2 \
     libglib2.0-0
+
+RUN apt install -y zip
+
+RUN wget "https://github.com/zachjs/sv2v/releases/download/v0.0.13/sv2v-Linux.zip" -O sv2v.zip
+RUN unzip sv2v.zip
+RUN mv sv2v-Linux/sv2v /usr/bin
+RUN rm sv2v.zip
+
+RUN wget "https://github.com/trabucayre/openFPGALoader/releases/download/v1.1.1/ubtuntu22.04-openFPGALoader.tgz" -O loader.tar.gz
+RUN tar -xvzf loader.tar.gz -C /
+
+RUN echo "export QT_QPA_PLATFORM=offscreen" >> ~/.bashrc
+RUN echo "export PATH=/IDE/bin:$PATH" >> ~/.bashrc
+RUN mkdir work
+WORKDIR /work
+
+RUN apt install -y kmod libhidapi-libusb0 libftdi1-2
+
+ENTRYPOINT ["/bin/bash", "-l", "-c"]

Makefile

@@ -0,0 +1,46 @@
+DCK=podman
+IMAGE_NAME=gowin
+WORKDIR=.
+
+DCK_VOLUMES=-v $(WORKDIR):/work
+DCK_RUN=$(DCK) run $(DCK_VOLUMES) $(IMAGE_NAME)
+DCK_RUN_IT=$(DCK) run $(DCK_VOLUMES) -it $(IMAGE_NAME)
+
+RTL_DIR=RTL/
+RTL_SV=$(shell find $(RTL_DIR) -name "*.sv")
+RTL_SVV = $(patsubst %.sv,%.v,$(RTL_SV))
+RTL_SOURCE=$(RTL_SVV) $(shell find $(RTL_DIR) -name "*.v")
+
+DEVICE_PATH=$(shell lsusb | grep "0403:6010" | sed -E "s/Bus ([0-9]{3}) Device ([0-9]{3}).*/\/dev\/bus\/usb\/\1\/\2/g")
+DCK_DEVICES=--device $(DEVICE_PATH)
+
+.PHONY: build_image bash clean
+
+## Build the container
+build_image:
+	$(DCK) build -t $(IMAGE_NAME) .
+
+## Get a bash shell inside the container
+bash:
+	$(DCK_RUN_IT) /bin/bash
+
+gw_sh:
+	$(DCK_RUN_IT) gw_sh
+
+impl/pnr/build.fs: $(RTL_SVV) build.tcl
+	$(DCK_RUN) "RTL_FILES=\"$(shell find $(RTL_DIR) -name *.v)\" gw_sh build.tcl"
+
+flash: impl/pnr/build.fs
+	if [ -z "$(DEVICE_PATH)" ]; then \
+		echo "Device not found."; \
+	else \
+		$(DCK) run --privileged --device /dev/bus/usb:/dev/bus/usb $(DCK_VOLUMES) gowin "openFPGALoader impl/pnr/build.fs"; \
+	fi
+
+%.v: %.sv
+	$(DCK_RUN) "sv2v --write=adjacent $<"
+
+clean: 
+	rm -rf $(RTL_SVV)
+	rm -rf impl
+

RTL/spade.sv

@@ -0,0 +1,298 @@
+`ifdef COCOTB_SIM
+    `define COCOTB_CODE(name) \
+        string __top_module; \
+        string __vcd_file; \
+        initial begin \
+            if ($value$plusargs("TOP_MODULE=%s", __top_module) && __top_module == `"name`" && $value$plusargs("VCD_FILENAME=%s", __vcd_file)) begin \
+                $dumpfile (__vcd_file); \
+                $dumpvars (0, \name ); \
+            end \
+        end
+`else
+    `define COCOTB_CODE(name)
+`endif
+
+
+module \std::cdc::sync2[1523]  (
+        input clk_i,
+        input input_i,
+        output output__
+    );
+    `COCOTB_CODE( std::cdc::sync2[1523] )
+    logic \clk ;
+    assign \clk  = clk_i;
+    logic \input ;
+    assign \input  = input_i;
+    (* src = "<compiler dir>/stdlib/cdc.spade:14,14" *)
+    reg \sync1 ;
+    (* src = "<compiler dir>/stdlib/cdc.spade:15,14" *)
+    reg \sync2 ;
+    always @(posedge \clk ) begin
+        \sync1  <= \input ;
+    end
+    always @(posedge \clk ) begin
+        \sync2  <= \sync1 ;
+    end
+    assign output__ = \sync2 ;
+endmodule
+
+
+module \std::cdc::sync2_bool  (
+        input clk_i,
+        input input_i,
+        output output__
+    );
+    `COCOTB_CODE( std::cdc::sync2_bool )
+    logic \clk ;
+    assign \clk  = clk_i;
+    logic \input ;
+    assign \input  = input_i;
+    (* src = "<compiler dir>/stdlib/cdc.spade:31,14" *)
+    logic _e_544;
+    (* src = "<compiler dir>/stdlib/cdc.spade:31,14" *)
+    
+    \std::cdc::sync2[1523]  \sync2_0 (.clk_i(\clk ), .input_i(\input ), .output__(_e_544));
+    assign output__ = _e_544;
+endmodule
+
+
+module \std::conv::tri_to_bool  (
+        input t_i,
+        output output__
+    );
+    `COCOTB_CODE( std::conv::tri_to_bool )
+    logic \t ;
+    assign \t  = t_i;
+    (* src = "<compiler dir>/stdlib/conv.spade:80,5" *)
+    logic _e_828;
+    (* src = "<compiler dir>/stdlib/conv.spade:80,5" *)
+    
+    \std::conv::impl#12::as_bool  \as_bool_0 (.self_i(\t ), .output__(_e_828));
+    assign output__ = _e_828;
+endmodule
+
+
+module \std::io::rising_edge  (
+        input clk_i,
+        input value_i,
+        output output__
+    );
+    `COCOTB_CODE( std::io::rising_edge )
+    logic \clk ;
+    assign \clk  = clk_i;
+    logic \value ;
+    assign \value  = value_i;
+    (* src = "<compiler dir>/stdlib/io.spade:12,14" *)
+    reg \old_value ;
+    (* src = "<compiler dir>/core/ops.spade:255,29" *)
+    logic _e_2136;
+    (* src = "<compiler dir>/core/ops.spade:255,9" *)
+    logic _e_2135;
+    (* src = "<compiler dir>/core/ops.spade:255,9" *)
+    logic _e_1034;
+    (* src = "<compiler dir>/core/ops.spade:297,29" *)
+    logic _e_2144;
+    (* src = "<compiler dir>/core/ops.spade:297,37" *)
+    logic _e_2145;
+    (* src = "<compiler dir>/core/ops.spade:297,9" *)
+    logic _e_2143;
+    (* src = "<compiler dir>/core/ops.spade:297,9" *)
+    logic _e_1032;
+    always @(posedge \clk ) begin
+        \old_value  <= \value ;
+    end
+    assign _e_2136 = {\old_value };
+    assign _e_2135 = ~_e_2136;
+    assign _e_1034 = _e_2135;
+    assign _e_2144 = {\value };
+    assign _e_2145 = {_e_1034};
+    assign _e_2143 = _e_2144 & _e_2145;
+    assign _e_1032 = _e_2143;
+    assign output__ = _e_1032;
+endmodule
+
+
+module \std::io::falling_edge  (
+        input clk_i,
+        input value_i,
+        output output__
+    );
+    `COCOTB_CODE( std::io::falling_edge )
+    logic \clk ;
+    assign \clk  = clk_i;
+    logic \value ;
+    assign \value  = value_i;
+    (* src = "<compiler dir>/stdlib/io.spade:27,14" *)
+    reg \old_value ;
+    (* src = "<compiler dir>/core/ops.spade:255,29" *)
+    logic _e_2154;
+    (* src = "<compiler dir>/core/ops.spade:255,9" *)
+    logic _e_2153;
+    (* src = "<compiler dir>/core/ops.spade:255,9" *)
+    logic _e_1041;
+    (* src = "<compiler dir>/core/ops.spade:297,29" *)
+    logic _e_2162;
+    (* src = "<compiler dir>/core/ops.spade:297,37" *)
+    logic _e_2163;
+    (* src = "<compiler dir>/core/ops.spade:297,9" *)
+    logic _e_2161;
+    (* src = "<compiler dir>/core/ops.spade:297,9" *)
+    logic _e_2160;
+    always @(posedge \clk ) begin
+        \old_value  <= \value ;
+    end
+    assign _e_2154 = {\value };
+    assign _e_2153 = ~_e_2154;
+    assign _e_1041 = _e_2153;
+    assign _e_2162 = {_e_1041};
+    assign _e_2163 = {\old_value };
+    assign _e_2161 = _e_2162 & _e_2163;
+    assign _e_2160 = _e_2161;
+    assign output__ = _e_2160;
+endmodule
+
+
+module main (
+        input clk,
+        output[3:0] leds
+    );
+    `COCOTB_CODE( main )
+    logic[3:0] \leds_mut ;
+    assign leds = \leds_mut ;
+    localparam[23:0] _e_1734 = 1;
+    (* src = "src/main.spade:4,34" *)
+    logic[23:0] _e_1732;
+    (* src = "src/main.spade:4,14" *)
+    reg[23:0] \counter ;
+    localparam[23:0] _e_1740 = 20;
+    (* src = "src/main.spade:6,16" *)
+    logic[23:0] _e_1738;
+    (* src = "src/main.spade:6,16" *)
+    logic[23:0] _e_1737;
+    (* src = "src/main.spade:6,16" *)
+    logic[3:0] _e_1736;
+    (* src = "src/main.spade:4,34" *)
+    
+    \core::ops::impl#77::wrapping_add[1524]  \wrapping_add_0 (.self_i(\counter ), .rhs_i(_e_1734), .output__(_e_1732));
+    always @(posedge \clk ) begin
+        \counter  <= _e_1732;
+    end
+    assign _e_1738 = \counter  >> _e_1740;
+    (* src = "src/main.spade:6,16" *)
+    
+    \std::conv::impl#14::as_bits[1525]  \as_bits_0 (.self_i(_e_1738), .output__(_e_1737));
+    assign _e_1736 = _e_1737[3-:4];
+    assign \leds_mut  = _e_1736;
+    
+endmodule
+
+
+module \std::conv::impl#10::as_clock  (
+        input self_i,
+        output output__
+    );
+    `COCOTB_CODE( std::conv::impl#10::as_clock )
+    logic \self ;
+    assign \self  = self_i;
+    logic _e_872;
+    assign _e_872 = \self ;
+    assign output__ = _e_872;
+endmodule
+
+
+module \std::conv::impl#10::as_uint  (
+        input self_i,
+        output output__
+    );
+    `COCOTB_CODE( std::conv::impl#10::as_uint )
+    logic \self ;
+    assign \self  = self_i;
+    logic _e_876;
+    assign _e_876 = \self ;
+    assign output__ = _e_876;
+endmodule
+
+
+module \std::conv::impl#11::as_bool  (
+        input self_i,
+        output output__
+    );
+    `COCOTB_CODE( std::conv::impl#11::as_bool )
+    logic \self ;
+    assign \self  = self_i;
+    logic _e_887;
+    assign _e_887 = \self ;
+    assign output__ = _e_887;
+endmodule
+
+
+module \std::conv::impl#12::as_bool  (
+        input self_i,
+        output output__
+    );
+    `COCOTB_CODE( std::conv::impl#12::as_bool )
+    logic \self ;
+    assign \self  = self_i;
+    logic _e_895;
+    assign _e_895 = \self ;
+    assign output__ = _e_895;
+endmodule
+
+
+module \std::conv::impl#14::as_bits[1525]  (
+        input[23:0] self_i,
+        output[23:0] output__
+    );
+    `COCOTB_CODE( std::conv::impl#14::as_bits[1525] )
+    logic[23:0] \self ;
+    assign \self  = self_i;
+    logic[23:0] _e_917;
+    assign _e_917 = \self ;
+    assign output__ = _e_917;
+endmodule
+
+
+module \std::default::impl#17::hacky_default  (
+        input self_i,
+        output output__
+    );
+    `COCOTB_CODE( std::default::impl#17::hacky_default )
+    logic \self ;
+    assign \self  = self_i;
+    localparam[0:0] _e_971 = 0;
+    assign output__ = _e_971;
+endmodule
+
+
+module \std::default::impl#18::hacky_default  (
+        
+    );
+    `COCOTB_CODE( std::default::impl#18::hacky_default )
+    
+endmodule
+
+
+module \core::ops::impl#77::wrapping_add[1524]  (
+        input[23:0] self_i,
+        input[23:0] rhs_i,
+        output[23:0] output__
+    );
+    `COCOTB_CODE( core::ops::impl#77::wrapping_add[1524] )
+    logic[23:0] \self ;
+    assign \self  = self_i;
+    logic[23:0] \rhs ;
+    assign \rhs  = rhs_i;
+    (* src = "<compiler dir>/core/ops.spade:166,62" *)
+    logic[24:0] _e_1883;
+    logic[24:0] \bits ;
+    (* src = "<compiler dir>/core/ops.spade:167,34" *)
+    logic[23:0] _e_1888;
+    logic[23:0] _e_1887;
+    assign _e_1883 = \self  + \rhs ;
+    assign \bits  = _e_1883;
+    assign _e_1888 = \bits [23-:24];
+    assign _e_1887 = _e_1888;
+    assign output__ = _e_1887;
+endmodule
+
+`default_nettype none

blinky/.gitignore

@@ -0,0 +1 @@
+build/

blinky/src/main.spade

@@ -0,0 +1,7 @@
+#[no_mangle(all)]
+entity main(clk: clock, leds: inv [bool; 4]) {
+
+    reg(clk) counter: uint<24> = counter +. 1;
+
+    set leds = (counter >> 20).as_bits()[0..4];
+}

blinky/swim.lock

@@ -0,0 +1,2 @@
+[spade]
+commit = "7dddfabc0c38800ebe097bfd2c88f85e63366831"

blinky/swim.toml

@@ -0,0 +1 @@
+name = "blinky"

build.tcl

@@ -0,0 +1,24 @@
+set_device GW5AST-LV138PG484AC1/I0 -name GW5AST-138C
+
+# Get project file from env
+set RTL_FILES $::env(RTL_FILES)
+
+# Add all files
+puts $RTL_FILES
+foreach rtl_file $RTL_FILES {
+    add_file $rtl_file
+}
+
+add_file pins.cst
+add_file test.sdc
+
+# Nom du module top
+set_option -top_module main
+set_option -global_freq 5
+
+# Répertoire de build
+set_option -output_base_name build
+
+# Étapes de compilation
+run syn
+run pnr

pins.cst

@@ -0,0 +1,453 @@
+
+//====== SYS  ====== 
+IO_LOC  "clk"   V22;
+IO_PORT "clk"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+#IO_LOC  "sys_rst_n" AA13;
+#IO_PORT "sys_rst_n" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+
+//====== OV5640 ====== 
+# IO_LOC  "cmos_pwdn" AB22;
+# IO_PORT "cmos_pwdn" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "cmos_rst_n" Y22;
+# IO_PORT "cmos_rst_n" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "cmos_xclk" AA21;
+# IO_PORT "cmos_xclk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=4 BANK_VCCIO=3.3;
+# IO_LOC  "cmos_sda" Y13;
+# IO_PORT "cmos_sda" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "cmos_scl" AA14;
+# IO_PORT "cmos_scl" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "cmos_db[7]" AA20;
+# IO_PORT "cmos_db[7]" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_db[6]" AA19;
+# IO_PORT "cmos_db[6]" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_db[5]" T20;
+# IO_PORT "cmos_db[5]" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_db[4]" N15;
+# IO_PORT "cmos_db[4]" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_db[3]" R14;
+# IO_PORT "cmos_db[3]" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_db[2]" R16;
+# IO_PORT "cmos_db[2]" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_db[1]" P15;
+# IO_PORT "cmos_db[1]" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_db[0]" P14;
+# IO_PORT "cmos_db[0]" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_pclk" AB20;
+# IO_PORT "cmos_pclk" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_href" AB21;
+# IO_PORT "cmos_href" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_LOC  "cmos_vsync" Y21;
+# IO_PORT "cmos_vsync" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+
+# //====== HDMI ====== 
+# IO_LOC  "tmds_d_p_0[0]" J14,H14;
+# IO_PORT "tmds_d_p_0[0]" PULL_MODE=NONE DRIVE=3.5;
+# IO_LOC  "tmds_d_p_0[1]" J15,H15;
+# IO_PORT "tmds_d_p_0[1]" PULL_MODE=NONE DRIVE=3.5;
+# IO_LOC  "tmds_d_p_0[2]" K17,J17;
+# IO_PORT "tmds_d_p_0[2]" PULL_MODE=NONE DRIVE=3.5;
+# IO_LOC  "tmds_clk_p_0"  G15,G16;
+# IO_PORT "tmds_clk_p_0"  PULL_MODE=NONE DRIVE=3.5;
+
+# //====== ETHERNET ====== 
+# IO_LOC  "RGMII_GTXCLK" 	F20;
+# IO_LOC  "PHY_CLK" 		V19;
+# IO_LOC  "RGMII_TXD[0]" 	D21;
+# IO_LOC  "RGMII_TXD[1]" 	E21;
+# IO_LOC  "RGMII_TXD[2]" 	D22;
+# IO_LOC  "RGMII_TXD[3]" 	E22;
+# IO_LOC  "RGMII_TXEN"  	F21;
+# IO_LOC  "RGMII_RST_N"  	W20;
+# IO_PORT "RGMII_GTXCLK"  IO_TYPE=LVCMOS33;
+# IO_PORT "PHY_CLK"       IO_TYPE=LVCMOS33;
+# IO_PORT "RGMII_TXD[0]"  IO_TYPE=LVCMOS33;
+# IO_PORT "RGMII_TXD[1]"  IO_TYPE=LVCMOS33;
+# IO_PORT "RGMII_TXD[2]"  IO_TYPE=LVCMOS33;
+# IO_PORT "RGMII_TXD[3]"  IO_TYPE=LVCMOS33;
+# IO_PORT "RGMII_TXEN"    IO_TYPE=LVCMOS33;
+# IO_PORT "RGMII_RST_N"   IO_TYPE=LVCMOS33;
+
+# //====== SDCARD ====== 
+# IO_LOC "sd_miso" 	AA15;
+# IO_LOC "sd_clk" 	V15;
+# IO_LOC "sd_cs" 	    W15;
+# IO_LOC "sd_mosi" 	Y16;
+# IO_PORT "sd_miso"   IO_TYPE=LVCMOS33;
+# IO_PORT "sd_clk"    IO_TYPE=LVCMOS33;
+# IO_PORT "sd_cs"     IO_TYPE=LVCMOS33;
+# IO_PORT "sd_mosi"   IO_TYPE=LVCMOS33;
+
+# //====== AUDIO ====== 
+# IO_LOC  "HP_BCK" 	Y17;
+# IO_LOC  "HP_WS" 	AB17;
+# IO_LOC  "HP_DIN" 	AA16;
+# IO_LOC  "PA_EN" 	AB16;
+# IO_PORT "HP_BCK"    IO_TYPE=LVCMOS33;
+# IO_PORT "HP_WS"     IO_TYPE=LVCMOS33;
+# IO_PORT "HP_DIN"    IO_TYPE=LVCMOS33;
+# IO_PORT "PA_EN"     IO_TYPE=LVCMOS33;
+
+# //====== Keys ====== 
+# IO_LOC  "Key_in[1]" Y12;
+# IO_LOC  "Key_in[0]" AB13;
+# IO_PORT "Key_in[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+# IO_PORT "Key_in[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+
+# //====== WS2812 ====== 
+# IO_LOC  "WS2812" J16;
+# IO_PORT "WS2812" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+
+# //====== Mic Array ====== 
+# IO_LOC  "sk9822_ck" W12;
+# IO_LOC  "sk9822_da" AA9;
+# IO_PORT "sk9822_ck" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_PORT "sk9822_da" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+
+# //====== LEDS ====== 
+# IO_LOC  "LED_o"   T18;
+IO_LOC  "leds[0]"   T18;
+IO_LOC  "leds[1]"   R18;
+IO_LOC  "leds[2]"   R17;
+IO_LOC  "leds[3]"   P16;
+# IO_LOC  "LEDs[4]"   U21;
+# IO_LOC  "LEDs[5]"   T21;
+# IO_LOC  "LEDs[6]"   R19;
+# IO_LOC  "LEDs[7]"   P19;
+
+# IO_PORT "LED_o"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+IO_PORT "leds[0]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+IO_PORT "leds[1]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+IO_PORT "leds[2]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+IO_PORT "leds[3]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "LEDs[4]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "LEDs[5]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "LEDs[6]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "LEDs[7]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+
+# //====== USBA ====== 
+# IO_LOC  "USB_1_P"   M15;
+# IO_LOC  "USB_1_N"   M16;
+# IO_LOC  "USB_2_P"   H13;
+# IO_LOC  "USB_2_N"   G13;
+
+# IO_PORT "USB_1_P"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "USB_1_N"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "USB_2_P"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "USB_2_N"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+
+# //====== JoyConA ====== 
+# IO_LOC  "Joycon_A[0]"   H19;
+# IO_LOC  "Joycon_A[1]"   H20;
+# IO_LOC  "Joycon_A[2]"   G20;
+# IO_LOC  "Joycon_A[3]"   M17;
+
+# IO_PORT "Joycon_A[0]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "Joycon_A[1]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "Joycon_A[2]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "Joycon_A[3]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+
+# //====== JoyConB ====== 
+# IO_LOC  "Joycon_B[0]"   H17;
+# IO_LOC  "Joycon_B[1]"   H18;
+# IO_LOC  "Joycon_B[2]"   J19;
+# IO_LOC  "Joycon_B[3]"   U8;
+
+# IO_PORT "Joycon_B[0]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "Joycon_B[1]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "Joycon_B[2]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "Joycon_B[3]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+
+# //====== LCD ====== 
+# IO_LOC  "LCD_CTP[0]"    W16;
+# IO_LOC  "LCD_CTP[1]"    U16;
+# IO_LOC  "LCD_CTP[2]"    T16;
+# IO_LOC  "LCD_CTP[3]"    T15;
+# IO_LOC  "LCD_BL"        P20;
+
+# IO_PORT "LCD_CTP[0]"    IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "LCD_CTP[1]"    IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "LCD_CTP[2]"    IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "LCD_CTP[3]"    IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+# IO_PORT "LCD_BL"        IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
+
+# //====== UART ====== 
+# IO_LOC  "txp"           U15;
+# IO_PORT "txp"           IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+
+# //For Version 31004 or later
+# IO_LOC  "rxp"           V14;
+# IO_PORT "rxp"           IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+
+# //For Version 31002
+# //IO_LOC  "rxp"           Y14;
+# //IO_PORT "rxp"           IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+
+# //====== CH569 ====== 
+# IO_LOC  "HSPI_HTCLK" J20;
+# IO_PORT "HSPI_HTCLK" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HTREQ" J21;
+# IO_PORT "HSPI_HTREQ" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HTRDY" L19;
+# IO_PORT "HSPI_HTRDY" PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HTVLD" G18;
+# IO_PORT "HSPI_HTVLD" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+
+# IO_LOC  "HSPI_HD[0]" G17;
+# IO_PORT "HSPI_HD[0]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[1]" H22;
+# IO_PORT "HSPI_HD[1]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[2]" L14;
+# IO_PORT "HSPI_HD[2]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[3]" K22;
+# IO_PORT "HSPI_HD[3]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[4]" K21;
+# IO_PORT "HSPI_HD[4]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[5]" K18;
+# IO_PORT "HSPI_HD[5]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[6]" L21;
+# IO_PORT "HSPI_HD[6]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[7]" M21;
+# IO_PORT "HSPI_HD[7]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[8]" M22;
+# IO_PORT "HSPI_HD[8]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[9]" N22;
+# IO_PORT "HSPI_HD[9]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[10]" L18;
+# IO_PORT "HSPI_HD[10]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[11]" M18;
+# IO_PORT "HSPI_HD[11]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[12]" N19;
+# IO_PORT "HSPI_HD[12]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[13]" N18;
+# IO_PORT "HSPI_HD[13]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[14]" K16;
+# IO_PORT "HSPI_HD[14]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "HSPI_HD[15]" L16;
+# IO_PORT "HSPI_HD[15]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+
+# //====== SDRAM ====== 
+# IO_LOC  "sdram_dqm[1]"  F13;
+# IO_PORT "sdram_dqm[1]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dqm[0]"  F14;
+# IO_PORT "sdram_dqm[0]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+
+# IO_LOC  "sdram_clk"     B17;
+# IO_PORT "sdram_clk"     IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_cas"     E17;
+# IO_PORT "sdram_cas"     IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_ras"     F16;
+# IO_PORT "sdram_ras"     IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_we"      D16;
+# IO_PORT "sdram_we"      IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_cs"      F19;
+# IO_PORT "sdram_cs"      IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_ba[1]"   C20;
+# IO_PORT "sdram_ba[1]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_ba[0]"   F15;
+# IO_PORT "sdram_ba[0]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+
+# IO_LOC  "sdram_adr[12]" B18;
+# IO_PORT "sdram_adr[12]" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[11]" D17;
+# IO_PORT "sdram_adr[11]" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[10]" D20;
+# IO_PORT "sdram_adr[10]" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[9]"  C17;
+# IO_PORT "sdram_adr[9]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[8]"  A18;
+# IO_PORT "sdram_adr[8]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[7]"  A19;
+# IO_PORT "sdram_adr[7]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[6]"  D14;
+# IO_PORT "sdram_adr[6]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[5]"  D15;
+# IO_PORT "sdram_adr[5]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[4]"  E16;
+# IO_PORT "sdram_adr[4]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[3]"  C18;
+# IO_PORT "sdram_adr[3]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[2]"  C19;
+# IO_PORT "sdram_adr[2]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[1]"  E19;
+# IO_PORT "sdram_adr[1]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_adr[0]"  D19;
+# IO_PORT "sdram_adr[0]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+
+# IO_LOC  "sdram_dq[15]"  B16;
+# IO_PORT "sdram_dq[15]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[14]"  B15;
+# IO_PORT "sdram_dq[14]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[13]"  A16;
+# IO_PORT "sdram_dq[13]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[12]"  A15;
+# IO_PORT "sdram_dq[12]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[11]"  A20;
+# IO_PORT "sdram_dq[11]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[10]"  B20;
+# IO_PORT "sdram_dq[10]"  IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[9]"   A21;
+# IO_PORT "sdram_dq[9]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[8]"   B21;
+# IO_PORT "sdram_dq[8]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[7]"   A13;
+# IO_PORT "sdram_dq[7]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[6]"   A14;
+# IO_PORT "sdram_dq[6]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[5]"   C13;
+# IO_PORT "sdram_dq[5]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[4]"   B13;
+# IO_PORT "sdram_dq[4]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[3]"   C14;
+# IO_PORT "sdram_dq[3]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[2]"   C15;
+# IO_PORT "sdram_dq[2]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[1]"   E13;
+# IO_PORT "sdram_dq[1]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+# IO_LOC  "sdram_dq[0]"   E14;
+# IO_PORT "sdram_dq[0]"   IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
+
+# //====== DDR3 ====== 
+# IO_LOC  "ddr_bank[2]"   M6;
+# IO_PORT "ddr_bank[2]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_bank[1]"   P2;
+# IO_PORT "ddr_bank[1]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_bank[0]"   P5;
+# IO_PORT "ddr_bank[0]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+
+# IO_LOC  "ddr_addr[15]"  R1;
+# IO_PORT "ddr_addr[15]"  IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[14]"  D1;
+# IO_PORT "ddr_addr[14]"  IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[13]"  K1;
+# IO_PORT "ddr_addr[13]"  IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[12]"  K4;
+# IO_PORT "ddr_addr[12]"  IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[11]"  H3;
+# IO_PORT "ddr_addr[11]"  IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[10]"  L1;
+# IO_PORT "ddr_addr[10]"  IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[9]"   H5;
+# IO_PORT "ddr_addr[9]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[8]"   J5;
+# IO_PORT "ddr_addr[8]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[7]"   J1;
+# IO_PORT "ddr_addr[7]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[6]"   G3;
+# IO_PORT "ddr_addr[6]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[5]"   H2;
+# IO_PORT "ddr_addr[5]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[4]"   J2;
+# IO_PORT "ddr_addr[4]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[3]"   J4;
+# IO_PORT "ddr_addr[3]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[2]"   G2;
+# IO_PORT "ddr_addr[2]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[1]"   K2;
+# IO_PORT "ddr_addr[1]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_addr[0]"   M1;
+# IO_PORT "ddr_addr[0]"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+
+# IO_LOC  "ddr_odt"       M2;
+# IO_PORT "ddr_odt"       IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_cke"       K6;
+# IO_PORT "ddr_cke"       IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_we"        M5;
+# IO_PORT "ddr_we"        IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_cas"       L4;
+# IO_PORT "ddr_cas"       IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_ras"       L5;
+# IO_PORT "ddr_ras"       IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_cs"        P4;
+# IO_PORT "ddr_cs"        IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_reset_n"   L6;
+# IO_PORT "ddr_reset_n"   IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_ck"        L3,K3;
+# IO_PORT "ddr_ck"        IO_TYPE=SSTL15D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dm[3]"     W1;
+# IO_PORT "ddr_dm[3]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dm[2]"     T6;
+# IO_PORT "ddr_dm[2]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dm[1]"     V7;
+# IO_PORT "ddr_dm[1]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dm[0]"     AA4;
+# IO_PORT "ddr_dm[0]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+
+# IO_LOC  "ddr_dq[31]"    Y2;
+# IO_PORT "ddr_dq[31]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[30]"    U1;
+# IO_PORT "ddr_dq[30]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[29]"    V2;
+# IO_PORT "ddr_dq[29]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[28]"    U2;
+# IO_PORT "ddr_dq[28]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[27]"    U3;
+# IO_PORT "ddr_dq[27]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[26]"    T1;
+# IO_PORT "ddr_dq[26]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[25]"    Y1;
+# IO_PORT "ddr_dq[25]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[24]"    W2;
+# IO_PORT "ddr_dq[24]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[23]"    T5;
+# IO_PORT "ddr_dq[23]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[22]"    V5;
+# IO_PORT "ddr_dq[22]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[21]"    T4;
+# IO_PORT "ddr_dq[21]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[20]"    Y6;
+# IO_PORT "ddr_dq[20]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[19]"    R4;
+# IO_PORT "ddr_dq[19]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[18]"    U6;
+# IO_PORT "ddr_dq[18]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[17]"    R6;
+# IO_PORT "ddr_dq[17]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[16]"    U5;
+# IO_PORT "ddr_dq[16]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[15]"    Y9;
+# IO_PORT "ddr_dq[15]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[14]"    AB6;
+# IO_PORT "ddr_dq[14]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[13]"    W9;
+# IO_PORT "ddr_dq[13]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[12]"    AB8;
+# IO_PORT "ddr_dq[12]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[11]"    Y7;
+# IO_PORT "ddr_dq[11]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[10]"    AB7;
+# IO_PORT "ddr_dq[10]"    IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[9]"     Y8;
+# IO_PORT "ddr_dq[9]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[8]"     AA8;
+# IO_PORT "ddr_dq[8]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[7]"     AB1;
+# IO_PORT "ddr_dq[7]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[6]"     AB5;
+# IO_PORT "ddr_dq[6]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[5]"     AB2;
+# IO_PORT "ddr_dq[5]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[4]"     AA1;
+# IO_PORT "ddr_dq[4]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[3]"     V4;
+# IO_PORT "ddr_dq[3]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[2]"     AA5;
+# IO_PORT "ddr_dq[2]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[1]"     AB3;
+# IO_PORT "ddr_dq[1]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dq[0]"     Y4;
+# IO_PORT "ddr_dq[0]"     IO_TYPE=SSTL15 PULL_MODE=NONE DRIVE=12 BANK_VCCIO=1.5;
+
+# IO_LOC  "ddr_dqs[3]"    R3,R2;
+# IO_PORT "ddr_dqs[3]"    IO_TYPE=SSTL15D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dqs[2]"    W6,W5;
+# IO_PORT "ddr_dqs[2]"    IO_TYPE=SSTL15D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dqs[1]"    V9,V8;
+# IO_PORT "ddr_dqs[1]"    IO_TYPE=SSTL15D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.5;
+# IO_LOC  "ddr_dqs[0]"    Y3,AA3;
+# IO_PORT "ddr_dqs[0]"    IO_TYPE=SSTL15D PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.5;
+
+# INS_LOC "camera_hdmi_inst/u_ddr3/gw3_top/u_ddr_phy_top/u_dll" DDRDLLM_BL;
+# INS_LOC "camera_hdmi_inst/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv" LEFTSIDE[4];
+# INS_LOC "camera_hdmi_inst/Gowin_PLL_m0/PLL_inst" PLL_L[0];
+# SET_PARAM "camera_hdmi_inst/u_ddr3/gw3_top/u_ddr_phy_top/u_dll" CLKIN_SEL=CLKIN5;
+

test.sdc

@@ -0,0 +1 @@
+create_clock -name clk -period 50.000 [get_ports { clk }]