18 lines
326 B
Verilog
18 lines
326 B
Verilog
module UartClockEnable (
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clock,
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reset,
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io_output_ce
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);
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input clock;
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input reset;
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output wire io_output_ce;
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reg [31:0] counter;
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wire [32:0] sum = {1'h0, counter} + 33'h00096feb5;
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always @(posedge clock)
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if (reset)
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counter <= 32'h00000000;
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else
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counter <= sum[31:0];
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assign io_output_ce = sum[32];
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endmodule
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