33 lines
1.5 KiB
Plaintext
33 lines
1.5 KiB
Plaintext
GowinSynthesis start
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Running parser ...
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Analyzing Verilog file '/work/RTL/spade.v'
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Analyzing Verilog file '/work/RTL/pll.v'
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Analyzing Verilog file '/work/RTL/gowin_pll_mod.v'
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Compiling module 'main'("/work/RTL/spade.v":114)
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Compiling module 'pll'("/work/RTL/gowin_pll_mod.v":2)
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Compiling module 'Gowin_PLL_MOD'("/work/RTL/gowin_pll_mod.v":56)
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Compiling module 'PLL_INIT(CLK_PERIOD=20,MULTI_FAC=15)'("/work/RTL/gowin_pll_mod.v":229)
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WARN (EX3791) : Expression size 5 truncated to fit in target size 4("/work/RTL/gowin_pll_mod.v":405)
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WARN (EX3791) : Expression size 18 truncated to fit in target size 17("/work/RTL/gowin_pll_mod.v":433)
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Compiling module 'core::ops::impl#77::wrapping_add[1533]'("/work/RTL/spade.v":284)
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NOTE (EX0101) : Current top module is "main"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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[95%] Generate netlist file "/work/impl/gwsynthesis/build.vg" completed
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[100%] Generate report file "/work/impl/gwsynthesis/build_syn.rpt.html" completed
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GowinSynthesis finish
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