32 lines
1.3 KiB
Plaintext
32 lines
1.3 KiB
Plaintext
Reading netlist file: "/work/impl/gwsynthesis/build.vg"
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Parsing netlist file "/work/impl/gwsynthesis/build.vg" completed
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Processing netlist completed
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Reading constraint file: "/work/pins.cst"
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Physical Constraint parsed completed
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Running placement......
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[10%] Placement Phase 0 completed
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[20%] Placement Phase 1 completed
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[30%] Placement Phase 2 completed
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WARN (TA1118) : the clock "clk"'s frequency does not match pll_0/u_pll/PLL_inst's param "FCLKIN = "50""
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[50%] Placement Phase 3 completed
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Running routing......
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[60%] Routing Phase 0 completed
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[70%] Routing Phase 1 completed
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[80%] Routing Phase 2 completed
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WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
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[90%] Routing Phase 3 completed
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Running timing analysis......
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[95%] Timing analysis completed
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Placement and routing completed
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Bitstream generation in progress......
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Bitstream generation completed
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Running power analysis......
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[100%] Power analysis completed
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Generate file "/work/impl/pnr/build.power.html" completed
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Generate file "/work/impl/pnr/build.pin.html" completed
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Generate file "/work/impl/pnr/build.rpt.html" completed
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Generate file "/work/impl/pnr/build.rpt.txt" completed
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Generate file "/work/impl/pnr/build.tr.html" completed
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Thu Jun 18 20:00:32 2026
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