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This commit is contained in:
Albin Chaboissier
2026-07-09 22:48:08 +02:00
parent 50dbc682d9
commit 49c9e6315b
56 changed files with 309162 additions and 2007410 deletions
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// Generated by CIRCT firtool-1.139.0
module AysncFifo(
input write_io_clk,
write_io_enq_valid,
input [7:0] write_io_enq_bits,
input read_io_clk,
read_io_deq_ready,
output read_io_deq_valid,
output [7:0] read_io_deq_bits
);
wire write_ready;
reg [10:0] write_ptr;
wire _GEN = write_ready & write_io_enq_valid;
reg [10:0] read_ptr;
reg [10:0] crossed_write_ptr_reg1;
reg [10:0] crossed_write_ptr_reg2;
wire _crossed_write_ptr_T_4 =
crossed_write_ptr_reg2[10] ^ crossed_write_ptr_reg2[9];
wire _crossed_write_ptr_T_6 = _crossed_write_ptr_T_4 ^ crossed_write_ptr_reg2[8];
wire _crossed_write_ptr_T_8 = _crossed_write_ptr_T_6 ^ crossed_write_ptr_reg2[7];
wire _crossed_write_ptr_T_10 =
_crossed_write_ptr_T_8 ^ crossed_write_ptr_reg2[6];
wire _crossed_write_ptr_T_12 =
_crossed_write_ptr_T_10 ^ crossed_write_ptr_reg2[5];
wire _crossed_write_ptr_T_14 =
_crossed_write_ptr_T_12 ^ crossed_write_ptr_reg2[4];
wire _crossed_write_ptr_T_16 =
_crossed_write_ptr_T_14 ^ crossed_write_ptr_reg2[3];
wire _crossed_write_ptr_T_18 =
_crossed_write_ptr_T_16 ^ crossed_write_ptr_reg2[2];
wire _crossed_write_ptr_T_20 =
_crossed_write_ptr_T_18 ^ crossed_write_ptr_reg2[1];
reg [10:0] crossed_read_ptr_reg1;
reg [10:0] crossed_read_ptr_reg2;
wire _crossed_read_ptr_T_4 =
crossed_read_ptr_reg2[10] ^ crossed_read_ptr_reg2[9];
wire _crossed_read_ptr_T_6 = _crossed_read_ptr_T_4 ^ crossed_read_ptr_reg2[8];
wire _crossed_read_ptr_T_8 = _crossed_read_ptr_T_6 ^ crossed_read_ptr_reg2[7];
wire _crossed_read_ptr_T_10 = _crossed_read_ptr_T_8 ^ crossed_read_ptr_reg2[6];
wire _crossed_read_ptr_T_12 = _crossed_read_ptr_T_10 ^ crossed_read_ptr_reg2[5];
wire _crossed_read_ptr_T_14 = _crossed_read_ptr_T_12 ^ crossed_read_ptr_reg2[4];
wire _crossed_read_ptr_T_16 = _crossed_read_ptr_T_14 ^ crossed_read_ptr_reg2[3];
wire _crossed_read_ptr_T_18 = _crossed_read_ptr_T_16 ^ crossed_read_ptr_reg2[2];
wire _crossed_read_ptr_T_20 = _crossed_read_ptr_T_18 ^ crossed_read_ptr_reg2[1];
wire _crossed_read_ptr_T_22 = _crossed_read_ptr_T_20 ^ crossed_read_ptr_reg2[0];
assign write_ready =
{crossed_read_ptr_reg2[10],
_crossed_read_ptr_T_4,
_crossed_read_ptr_T_6,
_crossed_read_ptr_T_8,
_crossed_read_ptr_T_10,
_crossed_read_ptr_T_12,
_crossed_read_ptr_T_14,
_crossed_read_ptr_T_16,
_crossed_read_ptr_T_18,
_crossed_read_ptr_T_20,
_crossed_read_ptr_T_22} == write_ptr
| {_crossed_read_ptr_T_4,
_crossed_read_ptr_T_6,
_crossed_read_ptr_T_8,
_crossed_read_ptr_T_10,
_crossed_read_ptr_T_12,
_crossed_read_ptr_T_14,
_crossed_read_ptr_T_16,
_crossed_read_ptr_T_18,
_crossed_read_ptr_T_20,
_crossed_read_ptr_T_22} != write_ptr[9:0];
wire read_valid =
{crossed_write_ptr_reg2[10],
_crossed_write_ptr_T_4,
_crossed_write_ptr_T_6,
_crossed_write_ptr_T_8,
_crossed_write_ptr_T_10,
_crossed_write_ptr_T_12,
_crossed_write_ptr_T_14,
_crossed_write_ptr_T_16,
_crossed_write_ptr_T_18,
_crossed_write_ptr_T_20,
_crossed_write_ptr_T_20 ^ crossed_write_ptr_reg2[0]} != read_ptr;
always @(posedge write_io_clk) begin
if (_GEN)
write_ptr <= write_ptr + 11'h1;
crossed_read_ptr_reg1 <= {read_ptr[10], read_ptr[9:0] ^ read_ptr[10:1]};
crossed_read_ptr_reg2 <= crossed_read_ptr_reg1;
end // always @(posedge)
always @(posedge read_io_clk) begin
if (read_io_deq_ready & read_valid)
read_ptr <= read_ptr + 11'h1;
crossed_write_ptr_reg1 <= {write_ptr[10], write_ptr[9:0] ^ write_ptr[10:1]};
crossed_write_ptr_reg2 <= crossed_write_ptr_reg1;
end // always @(posedge)
mem_1024x8 mem_ext (
.R0_addr (read_ptr[9:0]),
.R0_en (1'h1),
.R0_clk (read_io_clk),
.R0_data (read_io_deq_bits),
.W0_addr (write_ptr[9:0]),
.W0_en (_GEN),
.W0_clk (write_io_clk),
.W0_data (write_io_enq_bits)
);
assign read_io_deq_valid = read_valid;
endmodule

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module AysncFifo (
write_io_clk,
write_io_enq_valid,
write_io_enq_bits,
read_io_clk,
read_io_deq_ready,
read_io_deq_valid,
read_io_deq_bits
);
input write_io_clk;
input write_io_enq_valid;
input [7:0] write_io_enq_bits;
input read_io_clk;
input read_io_deq_ready;
output wire read_io_deq_valid;
output wire [7:0] read_io_deq_bits;
wire write_ready;
reg [10:0] write_ptr;
wire _GEN = write_ready & write_io_enq_valid;
reg [10:0] read_ptr;
reg [10:0] crossed_write_ptr_reg1;
reg [10:0] crossed_write_ptr_reg2;
wire _crossed_write_ptr_T_4 = crossed_write_ptr_reg2[10] ^ crossed_write_ptr_reg2[9];
wire _crossed_write_ptr_T_6 = _crossed_write_ptr_T_4 ^ crossed_write_ptr_reg2[8];
wire _crossed_write_ptr_T_8 = _crossed_write_ptr_T_6 ^ crossed_write_ptr_reg2[7];
wire _crossed_write_ptr_T_10 = _crossed_write_ptr_T_8 ^ crossed_write_ptr_reg2[6];
wire _crossed_write_ptr_T_12 = _crossed_write_ptr_T_10 ^ crossed_write_ptr_reg2[5];
wire _crossed_write_ptr_T_14 = _crossed_write_ptr_T_12 ^ crossed_write_ptr_reg2[4];
wire _crossed_write_ptr_T_16 = _crossed_write_ptr_T_14 ^ crossed_write_ptr_reg2[3];
wire _crossed_write_ptr_T_18 = _crossed_write_ptr_T_16 ^ crossed_write_ptr_reg2[2];
wire _crossed_write_ptr_T_20 = _crossed_write_ptr_T_18 ^ crossed_write_ptr_reg2[1];
reg [10:0] crossed_read_ptr_reg1;
reg [10:0] crossed_read_ptr_reg2;
wire _crossed_read_ptr_T_4 = crossed_read_ptr_reg2[10] ^ crossed_read_ptr_reg2[9];
wire _crossed_read_ptr_T_6 = _crossed_read_ptr_T_4 ^ crossed_read_ptr_reg2[8];
wire _crossed_read_ptr_T_8 = _crossed_read_ptr_T_6 ^ crossed_read_ptr_reg2[7];
wire _crossed_read_ptr_T_10 = _crossed_read_ptr_T_8 ^ crossed_read_ptr_reg2[6];
wire _crossed_read_ptr_T_12 = _crossed_read_ptr_T_10 ^ crossed_read_ptr_reg2[5];
wire _crossed_read_ptr_T_14 = _crossed_read_ptr_T_12 ^ crossed_read_ptr_reg2[4];
wire _crossed_read_ptr_T_16 = _crossed_read_ptr_T_14 ^ crossed_read_ptr_reg2[3];
wire _crossed_read_ptr_T_18 = _crossed_read_ptr_T_16 ^ crossed_read_ptr_reg2[2];
wire _crossed_read_ptr_T_20 = _crossed_read_ptr_T_18 ^ crossed_read_ptr_reg2[1];
wire _crossed_read_ptr_T_22 = _crossed_read_ptr_T_20 ^ crossed_read_ptr_reg2[0];
assign write_ready = ({crossed_read_ptr_reg2[10], _crossed_read_ptr_T_4, _crossed_read_ptr_T_6, _crossed_read_ptr_T_8, _crossed_read_ptr_T_10, _crossed_read_ptr_T_12, _crossed_read_ptr_T_14, _crossed_read_ptr_T_16, _crossed_read_ptr_T_18, _crossed_read_ptr_T_20, _crossed_read_ptr_T_22} == write_ptr) | ({_crossed_read_ptr_T_4, _crossed_read_ptr_T_6, _crossed_read_ptr_T_8, _crossed_read_ptr_T_10, _crossed_read_ptr_T_12, _crossed_read_ptr_T_14, _crossed_read_ptr_T_16, _crossed_read_ptr_T_18, _crossed_read_ptr_T_20, _crossed_read_ptr_T_22} != write_ptr[9:0]);
wire read_valid = {crossed_write_ptr_reg2[10], _crossed_write_ptr_T_4, _crossed_write_ptr_T_6, _crossed_write_ptr_T_8, _crossed_write_ptr_T_10, _crossed_write_ptr_T_12, _crossed_write_ptr_T_14, _crossed_write_ptr_T_16, _crossed_write_ptr_T_18, _crossed_write_ptr_T_20, _crossed_write_ptr_T_20 ^ crossed_write_ptr_reg2[0]} != read_ptr;
always @(posedge write_io_clk) begin
if (_GEN)
write_ptr <= write_ptr + 11'h001;
crossed_read_ptr_reg1 <= {read_ptr[10], read_ptr[9:0] ^ read_ptr[10:1]};
crossed_read_ptr_reg2 <= crossed_read_ptr_reg1;
end
always @(posedge read_io_clk) begin
if (read_io_deq_ready & read_valid)
read_ptr <= read_ptr + 11'h001;
crossed_write_ptr_reg1 <= {write_ptr[10], write_ptr[9:0] ^ write_ptr[10:1]};
crossed_write_ptr_reg2 <= crossed_write_ptr_reg1;
end
mem_1024x8 mem_ext(
.R0_addr(read_ptr[9:0]),
.R0_en(1'h1),
.R0_clk(read_io_clk),
.R0_data(read_io_deq_bits),
.W0_addr(write_ptr[9:0]),
.W0_en(_GEN),
.W0_clk(write_io_clk),
.W0_data(write_io_enq_bits)
);
assign read_io_deq_valid = read_valid;
endmodule

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// Generated by CIRCT firtool-1.139.0
module NIddr(
input clock,
input [3:0] io_input_data,
output [3:0] io_output_data_0,
io_output_data_1
);
wire _iddrs_3_Q0;
wire _iddrs_3_Q1;
wire _iddrs_2_Q0;
wire _iddrs_2_Q1;
wire _iddrs_1_Q0;
wire _iddrs_1_Q1;
wire _iddrs_0_Q0;
wire _iddrs_0_Q1;
IDDR iddrs_0 (
.CLK (clock),
.D (io_input_data[0]),
.Q0 (_iddrs_0_Q0),
.Q1 (_iddrs_0_Q1)
);
IDDR iddrs_1 (
.CLK (clock),
.D (io_input_data[1]),
.Q0 (_iddrs_1_Q0),
.Q1 (_iddrs_1_Q1)
);
IDDR iddrs_2 (
.CLK (clock),
.D (io_input_data[2]),
.Q0 (_iddrs_2_Q0),
.Q1 (_iddrs_2_Q1)
);
IDDR iddrs_3 (
.CLK (clock),
.D (io_input_data[3]),
.Q0 (_iddrs_3_Q0),
.Q1 (_iddrs_3_Q1)
);
assign io_output_data_0 = {_iddrs_3_Q0, _iddrs_2_Q0, _iddrs_1_Q0, _iddrs_0_Q0};
assign io_output_data_1 = {_iddrs_3_Q1, _iddrs_2_Q1, _iddrs_1_Q1, _iddrs_0_Q1};
endmodule

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module NIddr (
clock,
io_input_data,
io_output_data_0,
io_output_data_1
);
input clock;
input [3:0] io_input_data;
output wire [3:0] io_output_data_0;
output wire [3:0] io_output_data_1;
wire _iddrs_3_Q0;
wire _iddrs_3_Q1;
wire _iddrs_2_Q0;
wire _iddrs_2_Q1;
wire _iddrs_1_Q0;
wire _iddrs_1_Q1;
wire _iddrs_0_Q0;
wire _iddrs_0_Q1;
IDDR iddrs_0(
.CLK(clock),
.D(io_input_data[0]),
.Q0(_iddrs_0_Q0),
.Q1(_iddrs_0_Q1)
);
IDDR iddrs_1(
.CLK(clock),
.D(io_input_data[1]),
.Q0(_iddrs_1_Q0),
.Q1(_iddrs_1_Q1)
);
IDDR iddrs_2(
.CLK(clock),
.D(io_input_data[2]),
.Q0(_iddrs_2_Q0),
.Q1(_iddrs_2_Q1)
);
IDDR iddrs_3(
.CLK(clock),
.D(io_input_data[3]),
.Q0(_iddrs_3_Q0),
.Q1(_iddrs_3_Q1)
);
assign io_output_data_0 = {_iddrs_3_Q0, _iddrs_2_Q0, _iddrs_1_Q0, _iddrs_0_Q0};
assign io_output_data_1 = {_iddrs_3_Q1, _iddrs_2_Q1, _iddrs_1_Q1, _iddrs_0_Q1};
endmodule

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// Generated by CIRCT firtool-1.139.0
module NIddr_1(
input clock,
io_input_data,
output io_output_data_0
);
IDDR iddrs_0 (
.CLK (clock),
.D (io_input_data),
.Q0 (io_output_data_0),
.Q1 (/* unused */)
);
endmodule

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module NIddr_1 (
clock,
io_input_data,
io_output_data_0
);
input clock;
input io_input_data;
output wire io_output_data_0;
IDDR iddrs_0(
.CLK(clock),
.D(io_input_data),
.Q0(io_output_data_0),
.Q1()
);
endmodule

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// Generated by CIRCT firtool-1.139.0
module RgmiiReset(
input clock,
reset,
output io_ethernet_reset,
input io_pll_locked
);
reg [1:0] state;
reg timer;
wire _GEN = state == 2'h0;
wire _GEN_0 = state == 2'h1;
always @(posedge clock) begin
if (reset) begin
state <= 2'h0;
timer <= 1'h0;
end
else begin
if (_GEN)
state <= {1'h0, io_pll_locked};
timer <= ~_GEN & (_GEN_0 ? timer - 1'h1 : state == 2'h2 ? timer - 1'h1 : timer);
end
end // always @(posedge)
assign io_ethernet_reset = _GEN | _GEN_0 | state != 2'h2;
endmodule

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module RgmiiReset (
clock,
reset,
io_ethernet_reset,
io_pll_locked
);
input clock;
input reset;
output wire io_ethernet_reset;
input io_pll_locked;
reg [1:0] state;
reg timer;
wire _GEN = state == 2'h0;
wire _GEN_0 = state == 2'h1;
always @(posedge clock)
if (reset) begin
state <= 2'h0;
timer <= 1'h0;
end
else begin
if (_GEN)
state <= {1'h0, io_pll_locked};
timer <= ~_GEN & (_GEN_0 ? timer - 1'h1 : (state == 2'h2 ? timer - 1'h1 : timer));
end
assign io_ethernet_reset = (_GEN | _GEN_0) | (state != 2'h2);
endmodule

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// Generated by CIRCT firtool-1.139.0
module Top(
input clk,
irst,
output [3:0] leds,
output txp,
RGMII_GTXCLK,
PHY_CLK,
input RGMII_RXCK,
RGMII_RXD_0,
RGMII_RXD_1,
RGMII_RXD_2,
RGMII_RXD_3,
RGMII_RXDV,
output RGMII_RST_N,
RGMII_TXEN
);
wire _uart_tx_io_data_ready;
wire _uart_ce_io_output_ce;
wire _iddr_dv_io_output_data_0;
wire [3:0] _iddr_io_output_data_0;
wire [3:0] _iddr_io_output_data_1;
wire _byte_queue_read_io_deq_valid;
wire [7:0] _byte_queue_read_io_deq_bits;
wire _ethernet_clock_lock;
wire _rgmii_rxdv_dly2_DO;
wire _rgmii_rxdv_dly_DO;
wire _rgmii_rxd_dly2_3_DO;
wire _rgmii_rxd_dly1_3_DO;
wire _rgmii_rxd_dly2_2_DO;
wire _rgmii_rxd_dly1_2_DO;
wire _rgmii_rxd_dly2_1_DO;
wire _rgmii_rxd_dly1_1_DO;
wire _rgmii_rxd_dly2_DO;
wire _rgmii_rxd_dly1_DO;
wire [7:0] normal_byte = {_iddr_io_output_data_1, _iddr_io_output_data_0};
reg [3:0] skewed_byte_REG;
wire [7:0] skewed_byte = {_iddr_io_output_data_0, skewed_byte_REG};
reg normal_preamble_seen;
reg skewed_preamble_seen;
reg [1:0] ethernet_state;
wire _GEN = ethernet_state == 2'h0;
wire [3:0][7:0] _GEN_0 = {{8'h0}, {skewed_byte}, {normal_byte}, {8'h0}};
always @(posedge RGMII_RXCK) begin
skewed_byte_REG <= _iddr_io_output_data_1;
if (~irst) begin
normal_preamble_seen <= 1'h0;
skewed_preamble_seen <= 1'h0;
ethernet_state <= 2'h0;
end
else begin
automatic logic _GEN_1;
automatic logic _GEN_2;
automatic logic _GEN_3;
_GEN_1 = normal_preamble_seen & normal_byte == 8'hD5;
_GEN_2 = _GEN & _iddr_dv_io_output_data_0;
_GEN_3 = skewed_preamble_seen & skewed_byte == 8'hD5;
if (_GEN_2) begin
normal_preamble_seen <= ~_GEN_1 & (normal_byte == 8'h55 | normal_preamble_seen);
skewed_preamble_seen <= ~_GEN_3 & (skewed_byte == 8'h55 | skewed_preamble_seen);
end
if (_iddr_dv_io_output_data_0) begin
if (_GEN_2) begin
if (_GEN_3)
ethernet_state <= 2'h2;
else if (_GEN_1)
ethernet_state <= 2'h1;
end
end
else
ethernet_state <= 2'h0;
end
end // always @(posedge)
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1 (
.DI (RGMII_RXD_0),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly1_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2 (
.DI (_rgmii_rxd_dly1_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly2_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_1 (
.DI (RGMII_RXD_1),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly1_1_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_1 (
.DI (_rgmii_rxd_dly1_1_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly2_1_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_2 (
.DI (RGMII_RXD_2),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly1_2_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_2 (
.DI (_rgmii_rxd_dly1_2_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly2_2_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_3 (
.DI (RGMII_RXD_3),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly1_3_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_3 (
.DI (_rgmii_rxd_dly1_3_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxd_dly2_3_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxdv_dly (
.DI (RGMII_RXDV),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxdv_dly_DO),
.DF (/* unused */)
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(200),
.DYN_DLY_EN("FALSE")
) rgmii_rxdv_dly2 (
.DI (_rgmii_rxdv_dly_DO),
.SDTAP (1'h0),
.DLYSTEP (8'h0),
.VALUE (1'h0),
.DO (_rgmii_rxdv_dly2_DO),
.DF (/* unused */)
);
ether_pll ethernet_clock (
.clkin (clk),
.init_clk (clk),
.clkout0 (RGMII_GTXCLK),
.clkout1 (PHY_CLK),
.lock (_ethernet_clock_lock)
);
AysncFifo byte_queue (
.write_io_clk (RGMII_RXCK),
.write_io_enq_valid
(~(~_iddr_dv_io_output_data_0 | _GEN)
& (ethernet_state == 2'h1 | ethernet_state == 2'h2)),
.write_io_enq_bits (_GEN_0[ethernet_state]),
.read_io_clk (clk),
.read_io_deq_ready (_uart_tx_io_data_ready),
.read_io_deq_valid (_byte_queue_read_io_deq_valid),
.read_io_deq_bits (_byte_queue_read_io_deq_bits)
);
NIddr iddr (
.clock (RGMII_RXCK),
.io_input_data
({_rgmii_rxd_dly2_3_DO,
_rgmii_rxd_dly2_2_DO,
_rgmii_rxd_dly2_1_DO,
_rgmii_rxd_dly2_DO}),
.io_output_data_0 (_iddr_io_output_data_0),
.io_output_data_1 (_iddr_io_output_data_1)
);
NIddr_1 iddr_dv (
.clock (RGMII_RXCK),
.io_input_data (_rgmii_rxdv_dly2_DO),
.io_output_data_0 (_iddr_dv_io_output_data_0)
);
RgmiiReset ethernet_reset (
.clock (clk),
.reset (~irst),
.io_ethernet_reset (RGMII_RST_N),
.io_pll_locked (_ethernet_clock_lock)
);
UartClockEnable uart_ce (
.clock (clk),
.reset (~irst),
.io_output_ce (_uart_ce_io_output_ce)
);
UartTx uart_tx (
.clock (clk),
.reset (~irst),
.io_data_ready (_uart_tx_io_data_ready),
.io_data_valid (_byte_queue_read_io_deq_valid),
.io_data_bits (_byte_queue_read_io_deq_bits),
.io_signal (txp),
.io_clock_enable (_uart_ce_io_output_ce)
);
assign leds = 4'h0;
assign RGMII_TXEN = 1'h0;
endmodule

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module Top (
clk,
irst,
leds,
txp,
RGMII_GTXCLK,
PHY_CLK,
RGMII_RXCK,
RGMII_RXD_0,
RGMII_RXD_1,
RGMII_RXD_2,
RGMII_RXD_3,
RGMII_RXDV,
RGMII_RST_N,
RGMII_TXEN
);
input clk;
input irst;
output wire [3:0] leds;
output wire txp;
output wire RGMII_GTXCLK;
output wire PHY_CLK;
input RGMII_RXCK;
input RGMII_RXD_0;
input RGMII_RXD_1;
input RGMII_RXD_2;
input RGMII_RXD_3;
input RGMII_RXDV;
output wire RGMII_RST_N;
output wire RGMII_TXEN;
wire _uart_tx_io_data_ready;
wire _uart_ce_io_output_ce;
wire _iddr_dv_io_output_data_0;
wire [3:0] _iddr_io_output_data_0;
wire [3:0] _iddr_io_output_data_1;
wire _byte_queue_read_io_deq_valid;
wire [7:0] _byte_queue_read_io_deq_bits;
wire _ethernet_clock_lock;
wire _rgmii_rxdv_dly2_DO;
wire _rgmii_rxdv_dly_DO;
wire _rgmii_rxd_dly2_3_DO;
wire _rgmii_rxd_dly1_3_DO;
wire _rgmii_rxd_dly2_2_DO;
wire _rgmii_rxd_dly1_2_DO;
wire _rgmii_rxd_dly2_1_DO;
wire _rgmii_rxd_dly1_1_DO;
wire _rgmii_rxd_dly2_DO;
wire _rgmii_rxd_dly1_DO;
wire [7:0] normal_byte = {_iddr_io_output_data_1, _iddr_io_output_data_0};
reg [3:0] skewed_byte_REG;
wire [7:0] skewed_byte = {_iddr_io_output_data_0, skewed_byte_REG};
reg normal_preamble_seen;
reg skewed_preamble_seen;
reg [1:0] ethernet_state;
wire _GEN = ethernet_state == 2'h0;
wire [31:0] _GEN_0 = {8'h00, skewed_byte, normal_byte, 8'h00};
always @(posedge RGMII_RXCK) begin
skewed_byte_REG <= _iddr_io_output_data_1;
if (~irst) begin
normal_preamble_seen <= 1'h0;
skewed_preamble_seen <= 1'h0;
ethernet_state <= 2'h0;
end
else begin : sv2v_autoblock_1
reg _GEN_1;
reg _GEN_2;
reg _GEN_3;
_GEN_1 = normal_preamble_seen & (normal_byte == 8'hd5);
_GEN_2 = _GEN & _iddr_dv_io_output_data_0;
_GEN_3 = skewed_preamble_seen & (skewed_byte == 8'hd5);
if (_GEN_2) begin
normal_preamble_seen <= ~_GEN_1 & ((normal_byte == 8'h55) | normal_preamble_seen);
skewed_preamble_seen <= ~_GEN_3 & ((skewed_byte == 8'h55) | skewed_preamble_seen);
end
if (_iddr_dv_io_output_data_0) begin
if (_GEN_2) begin
if (_GEN_3)
ethernet_state <= 2'h2;
else if (_GEN_1)
ethernet_state <= 2'h1;
end
end
else
ethernet_state <= 2'h0;
end
end
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1(
.DI(RGMII_RXD_0),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxd_dly1_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2(
.DI(_rgmii_rxd_dly1_DO),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxd_dly2_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_1(
.DI(RGMII_RXD_1),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxd_dly1_1_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_1(
.DI(_rgmii_rxd_dly1_1_DO),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxd_dly2_1_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_2(
.DI(RGMII_RXD_2),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxd_dly1_2_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_2(
.DI(_rgmii_rxd_dly1_2_DO),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxd_dly2_2_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly1_3(
.DI(RGMII_RXD_3),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxd_dly1_3_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(52),
.DYN_DLY_EN("FALSE")
) rgmii_rxd_dly2_3(
.DI(_rgmii_rxd_dly1_3_DO),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxd_dly2_3_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(255),
.DYN_DLY_EN("FALSE")
) rgmii_rxdv_dly(
.DI(RGMII_RXDV),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxdv_dly_DO),
.DF()
);
IODELAY #(
.ADAPT_EN("FALSE"),
.C_STATIC_DLY(200),
.DYN_DLY_EN("FALSE")
) rgmii_rxdv_dly2(
.DI(_rgmii_rxdv_dly_DO),
.SDTAP(1'h0),
.DLYSTEP(8'h00),
.VALUE(1'h0),
.DO(_rgmii_rxdv_dly2_DO),
.DF()
);
ether_pll ethernet_clock(
.clkin(clk),
.init_clk(clk),
.clkout0(RGMII_GTXCLK),
.clkout1(PHY_CLK),
.lock(_ethernet_clock_lock)
);
AysncFifo byte_queue(
.write_io_clk(RGMII_RXCK),
.write_io_enq_valid(~(~_iddr_dv_io_output_data_0 | _GEN) & ((ethernet_state == 2'h1) | (ethernet_state == 2'h2))),
.write_io_enq_bits(_GEN_0[ethernet_state * 8+:8]),
.read_io_clk(clk),
.read_io_deq_ready(_uart_tx_io_data_ready),
.read_io_deq_valid(_byte_queue_read_io_deq_valid),
.read_io_deq_bits(_byte_queue_read_io_deq_bits)
);
NIddr iddr(
.clock(RGMII_RXCK),
.io_input_data({_rgmii_rxd_dly2_3_DO, _rgmii_rxd_dly2_2_DO, _rgmii_rxd_dly2_1_DO, _rgmii_rxd_dly2_DO}),
.io_output_data_0(_iddr_io_output_data_0),
.io_output_data_1(_iddr_io_output_data_1)
);
NIddr_1 iddr_dv(
.clock(RGMII_RXCK),
.io_input_data(_rgmii_rxdv_dly2_DO),
.io_output_data_0(_iddr_dv_io_output_data_0)
);
RgmiiReset ethernet_reset(
.clock(clk),
.reset(~irst),
.io_ethernet_reset(RGMII_RST_N),
.io_pll_locked(_ethernet_clock_lock)
);
UartClockEnable uart_ce(
.clock(clk),
.reset(~irst),
.io_output_ce(_uart_ce_io_output_ce)
);
UartTx uart_tx(
.clock(clk),
.reset(~irst),
.io_data_ready(_uart_tx_io_data_ready),
.io_data_valid(_byte_queue_read_io_deq_valid),
.io_data_bits(_byte_queue_read_io_deq_bits),
.io_signal(txp),
.io_clock_enable(_uart_ce_io_output_ce)
);
assign leds = 4'h0;
assign RGMII_TXEN = 1'h0;
endmodule

18
RTL/UartClockEnable.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module UartClockEnable(
input clock,
reset,
output io_output_ce
);
reg [31:0] counter;
wire [32:0] sum = {1'h0, counter} + 33'h96FEB5;
always @(posedge clock) begin
if (reset)
counter <= 32'h0;
else
counter <= sum[31:0];
end // always @(posedge)
assign io_output_ce = sum[32];
endmodule

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RTL/UartClockEnable.v Normal file
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module UartClockEnable (
clock,
reset,
io_output_ce
);
input clock;
input reset;
output wire io_output_ce;
reg [31:0] counter;
wire [32:0] sum = {1'h0, counter} + 33'h00096feb5;
always @(posedge clock)
if (reset)
counter <= 32'h00000000;
else
counter <= sum[31:0];
assign io_output_ce = sum[32];
endmodule

61
RTL/UartTx.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module UartTx(
input clock,
reset,
output io_data_ready,
input io_data_valid,
input [7:0] io_data_bits,
output io_signal,
input io_clock_enable
);
reg [1:0] state;
reg [7:0] data;
reg data_waiting;
reg [2:0] bit_counter;
reg [7:0] stop_bit_wait;
wire _GEN = state == 2'h0;
wire _GEN_0 = state == 2'h1;
wire _GEN_1 = state == 2'h2;
wire [7:0] _io_signal_T = data >> bit_counter;
always @(posedge clock) begin
automatic logic _GEN_2;
_GEN_2 = ~data_waiting & io_data_valid;
if (reset) begin
state <= 2'h0;
data_waiting <= 1'h0;
stop_bit_wait <= 8'h0;
end
else begin
automatic logic _GEN_3;
automatic logic _GEN_4;
automatic logic _GEN_5 = _GEN | _GEN_0 | _GEN_1;
_GEN_3 = stop_bit_wait == 8'h14;
_GEN_4 = (&state) & _GEN_3;
if (io_clock_enable) begin
automatic logic [3:0][1:0] _GEN_6;
_GEN_6 =
{{_GEN_4 ? 2'h0 : state},
{{1'h1, &bit_counter}},
{2'h2},
{{1'h0, data_waiting}}};
state <= _GEN_6[state];
end
data_waiting <= (~io_clock_enable | _GEN_5 | ~_GEN_4) & (_GEN_2 | data_waiting);
if (~io_clock_enable | _GEN_5 | ~(&state)) begin
end
else
stop_bit_wait <= _GEN_3 ? 8'h0 : stop_bit_wait + 8'h1;
end
if (_GEN_2)
data <= io_data_bits;
if (io_clock_enable) begin
automatic logic [3:0][2:0] _GEN_7 =
{{bit_counter}, {bit_counter + 3'h1}, {3'h0}, {bit_counter}};
bit_counter <= _GEN_7[state];
end
end // always @(posedge)
assign io_data_ready = ~data_waiting;
assign io_signal = _GEN | ~_GEN_0 & (~_GEN_1 | _io_signal_T[0]);
endmodule

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RTL/UartTx.v Normal file
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module UartTx (
clock,
reset,
io_data_ready,
io_data_valid,
io_data_bits,
io_signal,
io_clock_enable
);
input clock;
input reset;
output wire io_data_ready;
input io_data_valid;
input [7:0] io_data_bits;
output wire io_signal;
input io_clock_enable;
reg [1:0] state;
reg [7:0] data;
reg data_waiting;
reg [2:0] bit_counter;
reg [7:0] stop_bit_wait;
wire _GEN = state == 2'h0;
wire _GEN_0 = state == 2'h1;
wire _GEN_1 = state == 2'h2;
wire [7:0] _io_signal_T = data >> bit_counter;
always @(posedge clock) begin : sv2v_autoblock_1
reg _GEN_2;
_GEN_2 = ~data_waiting & io_data_valid;
if (reset) begin
state <= 2'h0;
data_waiting <= 1'h0;
stop_bit_wait <= 8'h00;
end
else begin : sv2v_autoblock_2
reg _GEN_3;
reg _GEN_4;
reg _GEN_5;
_GEN_5 = (_GEN | _GEN_0) | _GEN_1;
_GEN_3 = stop_bit_wait == 8'h14;
_GEN_4 = &state & _GEN_3;
if (io_clock_enable) begin : sv2v_autoblock_3
reg [7:0] _GEN_6;
_GEN_6 = {(_GEN_4 ? 2'h0 : state), 1'h1, &bit_counter, 3'h4, data_waiting};
state <= _GEN_6[state * 2+:2];
end
data_waiting <= ((~io_clock_enable | _GEN_5) | ~_GEN_4) & (_GEN_2 | data_waiting);
if ((~io_clock_enable | _GEN_5) | ~(&state))
;
else
stop_bit_wait <= (_GEN_3 ? 8'h00 : stop_bit_wait + 8'h01);
end
if (_GEN_2)
data <= io_data_bits;
if (io_clock_enable) begin : sv2v_autoblock_4
reg [11:0] _GEN_7;
_GEN_7 = {bit_counter, bit_counter + 3'h1, 3'h0, bit_counter};
bit_counter <= _GEN_7[state * 3+:3];
end
end
assign io_data_ready = ~data_waiting;
assign io_signal = _GEN | (~_GEN_0 & (~_GEN_1 | _io_signal_T[0]));
endmodule

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RTL/filelist.f Normal file
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mem_1024x8.sv
AysncFifo.sv
NIddr.sv
NIddr_1.sv
RgmiiReset.sv
UartClockEnable.sv
UartTx.sv
Top.sv

307200
RTL/gowin/finger.mem Normal file
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File diff suppressed because it is too large Load Diff

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RTL/gowin/pll.v Normal file
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`default_nettype wire
module normal_ra(
data_out,
addr,
clk,
ce,
rst
);
output reg [15:0] data_out;
input [19:0] addr;
input clk,ce,rst;
/* synthesis syn_ramstyle = "block_ram" */
reg [15:0] mem [614399:0] /* synthesis syn_ramstyle = "block_ram" */;
//reg [15:0] mem [2:0] /* synthesis syn_ramstyle = "block_ram" */;
initial begin
$readmemh("finger.mem", mem);
end
reg [19:0] reg_addr;
reg reg_ce;
always@(posedge clk) begin
reg_addr<=addr;
reg_ce<=ce;
if(rst) begin
reg_addr <= 0;
reg_ce <= 0;
data_out <= 0;
end
else if(reg_ce) begin
data_out <= mem[reg_addr];
end
end
endmodule
module oser10(
input [9:0] data,
input wire pclk,
input wire fclk,
input wire resetn,
output wire q
);
OSER10 uut(
.Q(q),
.D0(data[0]),
.D1(data[1]),
.D2(data[2]),
.D3(data[3]),
.D4(data[4]),
.D5(data[5]),
.D6(data[6]),
.D7(data[7]),
.D8(data[8]),
.D9(data[9]),
.PCLK(pclk),
.FCLK(fclk),
.RESET(resetn)
);
//defparam uut.GSREN="false";
//defparam uut.LSREN="true";
endmodule
module clkdiv(clkout, hclkin, resetn);
output clkout;
input hclkin;
input resetn;
wire gw_gnd;
assign gw_gnd = 1'b0;
CLKDIV clkdiv_inst (
.CLKOUT(clkout),
.HCLKIN(hclkin),
.RESETN(resetn),
.CALIB(gw_gnd)
);
defparam clkdiv_inst.DIV_MODE = "5";
endmodule //Gowin_CLKDIV
//Copyright (C)2014-2026 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//Tool Version: V1.9.12.02_SP2
//IP Version: 1.0
//Part Number: GW5AST-LV138PG484AC1/I0
//Device: GW5AST-138
//Device Version: C
//Created Time: Fri Jun 19 18:52:20 2026
module Gowin_PLL_MOD (lock, clkout0, clkin, reset, icpsel, lpfres, lpfcap);
output lock;
output clkout0;
input clkin;
input reset;
input [5:0] icpsel;
input [2:0] lpfres;
input [1:0] lpfcap;
wire clkout1;
wire clkout2;
wire clkout3;
wire clkout4;
wire clkout5;
wire clkout6;
wire clkfbout;
wire gw_vcc;
wire gw_gnd;
assign gw_vcc = 1'b1;
assign gw_gnd = 1'b0;
PLL PLL_inst (
.LOCK(lock),
.CLKOUT0(clkout0),
.CLKOUT1(clkout1),
.CLKOUT2(clkout2),
.CLKOUT3(clkout3),
.CLKOUT4(clkout4),
.CLKOUT5(clkout5),
.CLKOUT6(clkout6),
.CLKFBOUT(clkfbout),
.CLKIN(clkin),
.CLKFB(gw_gnd),
.RESET(reset),
.PLLPWD(gw_gnd),
.RESET_I(gw_gnd),
.RESET_O(gw_gnd),
.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL1({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL2({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL3({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL4({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL5({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL6({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT0({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT1({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT2({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT3({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ICPSEL(icpsel),
.LPFRES(lpfres),
.LPFCAP(lpfcap),
.PSSEL({gw_gnd,gw_gnd,gw_gnd}),
.PSDIR(gw_gnd),
.PSPULSE(gw_gnd),
.ENCLK0(gw_vcc),
.ENCLK1(gw_vcc),
.ENCLK2(gw_vcc),
.ENCLK3(gw_vcc),
.ENCLK4(gw_vcc),
.ENCLK5(gw_vcc),
.ENCLK6(gw_vcc),
.SSCPOL(gw_gnd),
.SSCON(gw_gnd),
.SSCMDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.SSCMDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd})
);
defparam PLL_inst.FCLKIN = "50";
defparam PLL_inst.IDIV_SEL = 1;
defparam PLL_inst.FBDIV_SEL = 3;
defparam PLL_inst.ODIV0_SEL = 6;
defparam PLL_inst.ODIV1_SEL = 8;
defparam PLL_inst.ODIV2_SEL = 8;
defparam PLL_inst.ODIV3_SEL = 8;
defparam PLL_inst.ODIV4_SEL = 8;
defparam PLL_inst.ODIV5_SEL = 8;
defparam PLL_inst.ODIV6_SEL = 8;
defparam PLL_inst.MDIV_SEL = 5;
defparam PLL_inst.MDIV_FRAC_SEL = 2;
defparam PLL_inst.ODIV0_FRAC_SEL = 2;
defparam PLL_inst.CLKOUT0_EN = "TRUE";
defparam PLL_inst.CLKOUT1_EN = "FALSE";
defparam PLL_inst.CLKOUT2_EN = "FALSE";
defparam PLL_inst.CLKOUT3_EN = "FALSE";
defparam PLL_inst.CLKOUT4_EN = "FALSE";
defparam PLL_inst.CLKOUT5_EN = "FALSE";
defparam PLL_inst.CLKOUT6_EN = "FALSE";
defparam PLL_inst.CLKFB_SEL = "INTERNAL";
defparam PLL_inst.CLKOUT0_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT1_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT2_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT3_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT0_DT_STEP = 0;
defparam PLL_inst.CLKOUT1_DT_STEP = 0;
defparam PLL_inst.CLKOUT2_DT_STEP = 0;
defparam PLL_inst.CLKOUT3_DT_STEP = 0;
defparam PLL_inst.CLK0_IN_SEL = 1'b0;
defparam PLL_inst.CLK0_OUT_SEL = 1'b0;
defparam PLL_inst.CLK1_IN_SEL = 1'b0;
defparam PLL_inst.CLK1_OUT_SEL = 1'b0;
defparam PLL_inst.CLK2_IN_SEL = 1'b0;
defparam PLL_inst.CLK2_OUT_SEL = 1'b0;
defparam PLL_inst.CLK3_IN_SEL = 1'b0;
defparam PLL_inst.CLK3_OUT_SEL = 1'b0;
defparam PLL_inst.CLK4_IN_SEL = 2'b00;
defparam PLL_inst.CLK4_OUT_SEL = 1'b0;
defparam PLL_inst.CLK5_IN_SEL = 1'b0;
defparam PLL_inst.CLK5_OUT_SEL = 1'b0;
defparam PLL_inst.CLK6_IN_SEL = 1'b0;
defparam PLL_inst.CLK6_OUT_SEL = 1'b0;
defparam PLL_inst.DYN_DPA_EN = "FALSE";
defparam PLL_inst.CLKOUT0_PE_COARSE = 0;
defparam PLL_inst.CLKOUT0_PE_FINE = 0;
defparam PLL_inst.CLKOUT1_PE_COARSE = 0;
defparam PLL_inst.CLKOUT1_PE_FINE = 0;
defparam PLL_inst.CLKOUT2_PE_COARSE = 0;
defparam PLL_inst.CLKOUT2_PE_FINE = 0;
defparam PLL_inst.CLKOUT3_PE_COARSE = 0;
defparam PLL_inst.CLKOUT3_PE_FINE = 0;
defparam PLL_inst.CLKOUT4_PE_COARSE = 0;
defparam PLL_inst.CLKOUT4_PE_FINE = 0;
defparam PLL_inst.CLKOUT5_PE_COARSE = 0;
defparam PLL_inst.CLKOUT5_PE_FINE = 0;
defparam PLL_inst.CLKOUT6_PE_COARSE = 0;
defparam PLL_inst.CLKOUT6_PE_FINE = 0;
defparam PLL_inst.DYN_PE0_SEL = "FALSE";
defparam PLL_inst.DYN_PE1_SEL = "FALSE";
defparam PLL_inst.DYN_PE2_SEL = "FALSE";
defparam PLL_inst.DYN_PE3_SEL = "FALSE";
defparam PLL_inst.DYN_PE4_SEL = "FALSE";
defparam PLL_inst.DYN_PE5_SEL = "FALSE";
defparam PLL_inst.DYN_PE6_SEL = "FALSE";
defparam PLL_inst.DE0_EN = "FALSE";
defparam PLL_inst.DE1_EN = "FALSE";
defparam PLL_inst.DE2_EN = "FALSE";
defparam PLL_inst.DE3_EN = "FALSE";
defparam PLL_inst.DE4_EN = "FALSE";
defparam PLL_inst.DE5_EN = "FALSE";
defparam PLL_inst.DE6_EN = "FALSE";
defparam PLL_inst.RESET_I_EN = "FALSE";
defparam PLL_inst.RESET_O_EN = "FALSE";
defparam PLL_inst.ICP_SEL = 6'bXXXXXX;
defparam PLL_inst.LPF_RES = 3'bXXX;
defparam PLL_inst.LPF_CAP = 2'b00;
defparam PLL_inst.SSC_EN = "FALSE";
defparam PLL_inst.DYN_IDIV_SEL = "FALSE";
defparam PLL_inst.DYN_FBDIV_SEL = "FALSE";
defparam PLL_inst.DYN_MDIV_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV0_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV1_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV2_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV3_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV4_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV5_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV6_SEL = "FALSE";
defparam PLL_inst.DYN_DT0_SEL = "FALSE";
defparam PLL_inst.DYN_DT1_SEL = "FALSE";
defparam PLL_inst.DYN_DT2_SEL = "FALSE";
defparam PLL_inst.DYN_DT3_SEL = "FALSE";
defparam PLL_inst.DYN_ICP_SEL = "TRUE";
defparam PLL_inst.DYN_LPF_SEL = "TRUE";
endmodule //Gowin_PLL_MOD
module pll(
clkin,
init_clk,
clkout0
);
input clkin;
input init_clk;
output clkout0;
wire lock;
wire [5:0] icpsel;
wire [2:0] lpfres;
wire pll_lock;
wire pll_rst;
Gowin_PLL_MOD u_pll(
.clkout0(clkout0),
.lock(pll_lock),
.clkin(clkin),
.reset(pll_rst),
.icpsel(icpsel),
.lpfres(lpfres),
.lpfcap(2'b00)
);
PLL_INIT u_pll_init(
.CLKIN(init_clk),
.I_RST(1'b0),
.O_RST(pll_rst),
.PLLLOCK(pll_lock),
.O_LOCK(lock),
.ICPSEL(icpsel),
.LPFRES(lpfres)
);
defparam u_pll_init.CLK_PERIOD = 20;
defparam u_pll_init.MULTI_FAC = 15;
endmodule
`timescale 1ns/1ns
module PLL_INIT
#(
parameter CLK_PERIOD = 50,
parameter MULTI_FAC = 30
)
(
input CLKIN,
input I_RST,
input PLLLOCK,
output O_RST,
output [5:0] ICPSEL,
output [2:0] LPFRES,
output O_LOCK
);
localparam WAIT_TIME = 'd2000_000;
localparam WAIT_CNT = (WAIT_TIME + CLK_PERIOD - 1) / CLK_PERIOD;
localparam WAIT_WIDTH = $clog2(WAIT_CNT + 1);
reg [WAIT_WIDTH-1:0] waitcnt = 'd0;
reg [3:0] RomAddr = 'd0;
reg [15:0] Rom [15:0];
reg [15:0] RomDreg ='d0;
wire [5:0] Regicp = RomDreg[5:0];
wire [2:0] Regres = RomDreg[10:8];
reg Waitlock = 'd0;
reg [7:0] locksig = 8'b0000_0000;
reg laststep = 1'b0;
wire validsig = RomDreg[12];
reg [1:0]enable_r = 2'b00;
wire Enable = enable_r[1];
always @(posedge CLKIN or posedge I_RST)
begin
if (I_RST)
enable_r <= 2'b00;
else
begin
enable_r <= {enable_r[0], 1'b1};
end
end
always @(posedge CLKIN or negedge Enable)
begin
if (Enable == 1'b0)
begin
RomDreg <= 16'h0000;
Rom[00] <= 16'h1400; //1
Rom[01] <= (MULTI_FAC > 34) ? 16'h1401
: (MULTI_FAC > 16) ? 16'h1400
: 16'h1400; //2
Rom[02] <= (MULTI_FAC > 34) ? 16'h1501
: (MULTI_FAC > 16) ? 16'h1500
: 16'h1500; //3
Rom[03] <= (MULTI_FAC > 34) ? 16'h1503
: (MULTI_FAC > 16) ? 16'h1501
: 16'h1500; //4
Rom[04] <= (MULTI_FAC > 34) ? 16'h1507
: (MULTI_FAC > 16) ? 16'h1503
: 16'h1501; //5
Rom[05] <= (MULTI_FAC > 34) ? 16'h0605
: (MULTI_FAC > 16) ? 16'h0602
: 16'h0601; //6
Rom[06] <= 16'h0000; //over
Rom[07] <= (MULTI_FAC > 34) ? 16'h1402
: (MULTI_FAC > 16) ? 16'h1401
: 16'h1400; //2.5
Rom[08] <= (MULTI_FAC > 34) ? 16'h1502
: (MULTI_FAC > 16) ? 16'h1501
: 16'h1500; //3.5
Rom[09] <= (MULTI_FAC > 34) ? 16'h1504
: (MULTI_FAC > 16) ? 16'h1502
: 16'h1501; //4.5
Rom[10] <= (MULTI_FAC > 34) ? 16'h1603
: (MULTI_FAC > 16) ? 16'h1601
: 16'h1600; //5.5
Rom[11] <= 16'h1400; //1.5
Rom[12] <= 16'h0000;
Rom[13] <= 16'h0000;
Rom[14] <= 16'h0000;
Rom[15] <= 16'h0000;
end
else
RomDreg <= Rom[RomAddr[3:0]];
end
reg [3:0]RomAddrVld = 'd0;
always @ (*) begin
casex (locksig[5:0])
6'b111_111 : RomAddrVld = 4'd8;
6'b011_111 : RomAddrVld = 4'd8;
6'b111_110 : RomAddrVld = 4'd8;
6'b111_10x : RomAddrVld = 4'd9;
6'bx01_111 : RomAddrVld = 4'd7;
6'b011_110 : RomAddrVld = 4'd8;
6'bxx0_111 : RomAddrVld = 4'd1;
6'bx01_110 : RomAddrVld = 4'd2;
6'b011_10x : RomAddrVld = 4'd3;
6'b111_0xx : RomAddrVld = 4'd4;
6'bxxx_011 : RomAddrVld = 4'd1;
6'bxx0_110 : RomAddrVld = 4'd7;
6'bx01_100 : RomAddrVld = 4'd8;
6'b011_000 : RomAddrVld = 4'd9;
6'b110_000 : RomAddrVld = 4'd10;
6'bxxx_x01 : RomAddrVld = 4'd0;
6'bxxx_010 : RomAddrVld = 4'd1;
6'bxx0_100 : RomAddrVld = 4'd2;
6'bx01_000 : RomAddrVld = 4'd3;
6'b010_000 : RomAddrVld = 4'd4;
6'b100_000 : RomAddrVld = 4'd5;
6'b000_000 : RomAddrVld = 4'd8;
default : RomAddrVld = 4'd8;
endcase
end
reg [3:0]state='d0;
localparam IDLE = 4'd0;
localparam STATE1 = 4'd1;
localparam STATE2 = 4'd2;
localparam STATE3 = 4'd3;
localparam STATE4 = 4'd4;
localparam STATE5 = 4'd5;
localparam STATE6 = 4'd6;
localparam STATE7 = 4'd7;
always @(posedge CLKIN or negedge Enable)
begin
if (Enable == 1'b0)
begin
state <= IDLE;
RomAddr<=4'b0000;
laststep <= 1'b0;
end
else
begin
case (state)
IDLE:
begin
state<=STATE1;
end
STATE1:
begin
state<=STATE2;
end
STATE2:
begin
if (laststep==1'b1)
state<=STATE7;
else
state<=STATE3;
end
STATE3:
begin
if (Waitlock==1'b1)
state<=STATE4;
else
state<= STATE3;
end
STATE4:
begin
state<=STATE5;
end
STATE5:
begin
if (validsig==1'b1)
begin
RomAddr <= RomAddr + 1;
state <= STATE1;
end
else if (validsig==1'b0 && laststep==1'b0)
state <= STATE6;
end
STATE6:
begin
RomAddr <= RomAddrVld;
laststep <= 1'b1;
state <= STATE1;
end
STATE7:
begin
state<=STATE7;
end
default: state<=IDLE;
endcase
end
end
always @(posedge CLKIN)
begin
Waitlock <= (&waitcnt == 1'b1) ? 1'b1 : 1'b0;
waitcnt <= (state==STATE3) ? (waitcnt+1) : 'd0;
if (~Enable) locksig <= 8'b0000_0000;
else if (state==STATE4) locksig[RomAddr[3:0]] <= PLLLOCK;
end
assign ICPSEL = Regicp;
assign LPFRES = Regres;
assign O_RST = (~Enable) || (state==STATE2) ? 1'b1 : 1'b0;
assign O_LOCK = (state==STATE7) ? PLLLOCK : 1'b0;
endmodule
module ether_pll(
clkin,
init_clk,
clkout0,
clkout1,
lock
);
input clkin;
input init_clk;
output clkout0;
output clkout1;
output lock;
wire [5:0] icpsel;
wire [2:0] lpfres;
wire pll_lock;
wire pll_rst;
Gowin_PLL_MOD_ether u_pll(
.clkout1(clkout1),
.clkout0(clkout0),
.lock(pll_lock),
.clkin(clkin),
.reset(pll_rst),
.icpsel(icpsel),
.lpfres(lpfres),
.lpfcap(2'b00)
);
PLL_INIT u_pll_init(
.CLKIN(init_clk),
.I_RST(1'b0),
.O_RST(pll_rst),
.PLLLOCK(pll_lock),
.O_LOCK(lock),
.ICPSEL(icpsel),
.LPFRES(lpfres)
);
defparam u_pll_init.CLK_PERIOD = 20;
defparam u_pll_init.MULTI_FAC = 15;
endmodule
module Gowin_PLL_MOD_ether (lock, clkout0, clkout1, clkin, reset, icpsel, lpfres, lpfcap);
output lock;
output clkout0;
output clkout1;
input clkin;
input reset;
input [5:0] icpsel;
input [2:0] lpfres;
input [1:0] lpfcap;
wire clkout2;
wire clkout3;
wire clkout4;
wire clkout5;
wire clkout6;
wire clkfbout;
wire gw_vcc;
wire gw_gnd;
assign gw_vcc = 1'b1;
assign gw_gnd = 1'b0;
PLL PLL_inst (
.LOCK(lock),
.CLKOUT0(clkout0),
.CLKOUT1(clkout1),
.CLKOUT2(clkout2),
.CLKOUT3(clkout3),
.CLKOUT4(clkout4),
.CLKOUT5(clkout5),
.CLKOUT6(clkout6),
.CLKFBOUT(clkfbout),
.CLKIN(clkin),
.CLKFB(gw_gnd),
.RESET(reset),
.PLLPWD(gw_gnd),
.RESET_I(gw_gnd),
.RESET_O(gw_gnd),
.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL1({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL2({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL3({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL4({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL5({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL6({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT0({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT1({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT2({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT3({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ICPSEL(icpsel),
.LPFRES(lpfres),
.LPFCAP(lpfcap),
.PSSEL({gw_gnd,gw_gnd,gw_gnd}),
.PSDIR(gw_gnd),
.PSPULSE(gw_gnd),
.ENCLK0(gw_vcc),
.ENCLK1(gw_vcc),
.ENCLK2(gw_vcc),
.ENCLK3(gw_vcc),
.ENCLK4(gw_vcc),
.ENCLK5(gw_vcc),
.ENCLK6(gw_vcc),
.SSCPOL(gw_gnd),
.SSCON(gw_gnd),
.SSCMDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.SSCMDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd})
);
defparam PLL_inst.FCLKIN = "50";
defparam PLL_inst.IDIV_SEL = 1;
defparam PLL_inst.FBDIV_SEL = 1;
defparam PLL_inst.ODIV0_SEL = 6;
defparam PLL_inst.ODIV1_SEL = 30;
defparam PLL_inst.ODIV2_SEL = 8;
defparam PLL_inst.ODIV3_SEL = 8;
defparam PLL_inst.ODIV4_SEL = 8;
defparam PLL_inst.ODIV5_SEL = 8;
defparam PLL_inst.ODIV6_SEL = 8;
defparam PLL_inst.MDIV_SEL = 15;
defparam PLL_inst.MDIV_FRAC_SEL = 0;
defparam PLL_inst.ODIV0_FRAC_SEL = 0;
defparam PLL_inst.CLKOUT0_EN = "TRUE";
defparam PLL_inst.CLKOUT1_EN = "TRUE";
defparam PLL_inst.CLKOUT2_EN = "FALSE";
defparam PLL_inst.CLKOUT3_EN = "FALSE";
defparam PLL_inst.CLKOUT4_EN = "FALSE";
defparam PLL_inst.CLKOUT5_EN = "FALSE";
defparam PLL_inst.CLKOUT6_EN = "FALSE";
defparam PLL_inst.CLKFB_SEL = "INTERNAL";
defparam PLL_inst.CLKOUT0_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT1_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT2_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT3_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT0_DT_STEP = 0;
defparam PLL_inst.CLKOUT1_DT_STEP = 0;
defparam PLL_inst.CLKOUT2_DT_STEP = 0;
defparam PLL_inst.CLKOUT3_DT_STEP = 0;
defparam PLL_inst.CLK0_IN_SEL = 1'b0;
defparam PLL_inst.CLK0_OUT_SEL = 1'b0;
defparam PLL_inst.CLK1_IN_SEL = 1'b0;
defparam PLL_inst.CLK1_OUT_SEL = 1'b0;
defparam PLL_inst.CLK2_IN_SEL = 1'b0;
defparam PLL_inst.CLK2_OUT_SEL = 1'b0;
defparam PLL_inst.CLK3_IN_SEL = 1'b0;
defparam PLL_inst.CLK3_OUT_SEL = 1'b0;
defparam PLL_inst.CLK4_IN_SEL = 2'b00;
defparam PLL_inst.CLK4_OUT_SEL = 1'b0;
defparam PLL_inst.CLK5_IN_SEL = 1'b0;
defparam PLL_inst.CLK5_OUT_SEL = 1'b0;
defparam PLL_inst.CLK6_IN_SEL = 1'b0;
defparam PLL_inst.CLK6_OUT_SEL = 1'b0;
defparam PLL_inst.DYN_DPA_EN = "FALSE";
defparam PLL_inst.CLKOUT0_PE_COARSE = 0;
defparam PLL_inst.CLKOUT0_PE_FINE = 0;
defparam PLL_inst.CLKOUT1_PE_COARSE = 0;
defparam PLL_inst.CLKOUT1_PE_FINE = 0;
defparam PLL_inst.CLKOUT2_PE_COARSE = 0;
defparam PLL_inst.CLKOUT2_PE_FINE = 0;
defparam PLL_inst.CLKOUT3_PE_COARSE = 0;
defparam PLL_inst.CLKOUT3_PE_FINE = 0;
defparam PLL_inst.CLKOUT4_PE_COARSE = 0;
defparam PLL_inst.CLKOUT4_PE_FINE = 0;
defparam PLL_inst.CLKOUT5_PE_COARSE = 0;
defparam PLL_inst.CLKOUT5_PE_FINE = 0;
defparam PLL_inst.CLKOUT6_PE_COARSE = 0;
defparam PLL_inst.CLKOUT6_PE_FINE = 0;
defparam PLL_inst.DYN_PE0_SEL = "FALSE";
defparam PLL_inst.DYN_PE1_SEL = "FALSE";
defparam PLL_inst.DYN_PE2_SEL = "FALSE";
defparam PLL_inst.DYN_PE3_SEL = "FALSE";
defparam PLL_inst.DYN_PE4_SEL = "FALSE";
defparam PLL_inst.DYN_PE5_SEL = "FALSE";
defparam PLL_inst.DYN_PE6_SEL = "FALSE";
defparam PLL_inst.DE0_EN = "FALSE";
defparam PLL_inst.DE1_EN = "FALSE";
defparam PLL_inst.DE2_EN = "FALSE";
defparam PLL_inst.DE3_EN = "FALSE";
defparam PLL_inst.DE4_EN = "FALSE";
defparam PLL_inst.DE5_EN = "FALSE";
defparam PLL_inst.DE6_EN = "FALSE";
defparam PLL_inst.RESET_I_EN = "FALSE";
defparam PLL_inst.RESET_O_EN = "FALSE";
defparam PLL_inst.ICP_SEL = 6'bXXXXXX;
defparam PLL_inst.LPF_RES = 3'bXXX;
defparam PLL_inst.LPF_CAP = 2'b00;
defparam PLL_inst.SSC_EN = "FALSE";
defparam PLL_inst.DYN_IDIV_SEL = "FALSE";
defparam PLL_inst.DYN_FBDIV_SEL = "FALSE";
defparam PLL_inst.DYN_MDIV_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV0_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV1_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV2_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV3_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV4_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV5_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV6_SEL = "FALSE";
defparam PLL_inst.DYN_DT0_SEL = "FALSE";
defparam PLL_inst.DYN_DT1_SEL = "FALSE";
defparam PLL_inst.DYN_DT2_SEL = "FALSE";
defparam PLL_inst.DYN_DT3_SEL = "FALSE";
defparam PLL_inst.DYN_ICP_SEL = "TRUE";
defparam PLL_inst.DYN_LPF_SEL = "TRUE";
endmodule //Gowin_PLL_MOD
module gowin_ddr(
din,
clk,
q
)
;
input [7:0] din;
input clk;
output [3:0] q;
wire \oddr_gen[0].oddr_inst_1_Q1 ;
wire \oddr_gen[1].oddr_inst_1_Q1 ;
wire \oddr_gen[2].oddr_inst_1_Q1 ;
wire \oddr_gen[3].oddr_inst_1_Q1 ;
wire VCC;
wire GND;
ODDR \oddr_gen[0].oddr_inst (
.Q0(q[0]),
.Q1(\oddr_gen[0].oddr_inst_1_Q1 ),
.D0(din[0]),
.D1(din[4]),
.TX(GND),
.CLK(clk)
);
ODDR \oddr_gen[1].oddr_inst (
.Q0(q[1]),
.Q1(\oddr_gen[1].oddr_inst_1_Q1 ),
.D0(din[1]),
.D1(din[5]),
.TX(GND),
.CLK(clk)
);
ODDR \oddr_gen[2].oddr_inst (
.Q0(q[2]),
.Q1(\oddr_gen[2].oddr_inst_1_Q1 ),
.D0(din[2]),
.D1(din[6]),
.TX(GND),
.CLK(clk)
);
ODDR \oddr_gen[3].oddr_inst (
.Q0(q[3]),
.Q1(\oddr_gen[3].oddr_inst_1_Q1 ),
.D0(din[3]),
.D1(din[7]),
.TX(GND),
.CLK(clk)
);
VCC VCC_cZ (
.V(VCC)
);
GND GND_cZ (
.G(GND)
);
GSR GSR (
.GSRI(VCC)
);
endmodule /* Gowin_DDR */

446
RTL/gowin_pll_mod.v
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@ -1,446 +0,0 @@
`default_nettype wire
module pll(
clkin,
init_clk,
clkout0,
lock
);
input clkin;
input init_clk;
output clkout0;
output lock;
wire [5:0] icpsel;
wire [2:0] lpfres;
wire pll_lock;
wire pll_rst;
Gowin_PLL_MOD u_pll(
.clkout0(clkout0),
.lock(pll_lock),
.clkin(clkin),
.reset(pll_rst),
.icpsel(icpsel),
.lpfres(lpfres),
.lpfcap(2'b00)
);
PLL_INIT u_pll_init(
.CLKIN(init_clk),
.I_RST(1'b0),
.O_RST(pll_rst),
.PLLLOCK(pll_lock),
.O_LOCK(lock),
.ICPSEL(icpsel),
.LPFRES(lpfres)
);
defparam u_pll_init.CLK_PERIOD = 20;
defparam u_pll_init.MULTI_FAC = 15;
endmodule
//Copyright (C)2014-2026 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//Tool Version: V1.9.12.02_SP2
//IP Version: 1.0
//Part Number: GW5AST-LV138PG484AC1/I0
//Device: GW5AST-138
//Device Version: C
//Created Time: Thu Jun 18 20:59:31 2026
module Gowin_PLL_MOD (lock, clkout0, clkin, reset, icpsel, lpfres, lpfcap);
output lock;
output clkout0;
input clkin;
input reset;
input [5:0] icpsel;
input [2:0] lpfres;
input [1:0] lpfcap;
wire clkout1;
wire clkout2;
wire clkout3;
wire clkout4;
wire clkout5;
wire clkout6;
wire clkfbout;
wire gw_vcc;
wire gw_gnd;
assign gw_vcc = 1'b1;
assign gw_gnd = 1'b0;
PLL PLL_inst (
.LOCK(lock),
.CLKOUT0(clkout0),
.CLKOUT1(clkout1),
.CLKOUT2(clkout2),
.CLKOUT3(clkout3),
.CLKOUT4(clkout4),
.CLKOUT5(clkout5),
.CLKOUT6(clkout6),
.CLKFBOUT(clkfbout),
.CLKIN(clkin),
.CLKFB(gw_gnd),
.RESET(reset),
.PLLPWD(gw_gnd),
.RESET_I(gw_gnd),
.RESET_O(gw_gnd),
.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.MDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL0_FRAC({gw_gnd,gw_gnd,gw_gnd}),
.ODSEL1({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL2({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL3({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL4({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL5({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL6({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT0({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT1({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT2({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DT3({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ICPSEL(icpsel),
.LPFRES(lpfres),
.LPFCAP(lpfcap),
.PSSEL({gw_gnd,gw_gnd,gw_gnd}),
.PSDIR(gw_gnd),
.PSPULSE(gw_gnd),
.ENCLK0(gw_vcc),
.ENCLK1(gw_vcc),
.ENCLK2(gw_vcc),
.ENCLK3(gw_vcc),
.ENCLK4(gw_vcc),
.ENCLK5(gw_vcc),
.ENCLK6(gw_vcc),
.SSCPOL(gw_gnd),
.SSCON(gw_gnd),
.SSCMDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.SSCMDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd})
);
defparam PLL_inst.FCLKIN = "50";
defparam PLL_inst.IDIV_SEL = 1;
defparam PLL_inst.FBDIV_SEL = 3;
defparam PLL_inst.ODIV0_SEL = 31;
defparam PLL_inst.ODIV1_SEL = 8;
defparam PLL_inst.ODIV2_SEL = 8;
defparam PLL_inst.ODIV3_SEL = 8;
defparam PLL_inst.ODIV4_SEL = 8;
defparam PLL_inst.ODIV5_SEL = 8;
defparam PLL_inst.ODIV6_SEL = 8;
defparam PLL_inst.MDIV_SEL = 5;
defparam PLL_inst.MDIV_FRAC_SEL = 2;
defparam PLL_inst.ODIV0_FRAC_SEL = 2;
defparam PLL_inst.CLKOUT0_EN = "TRUE";
defparam PLL_inst.CLKOUT1_EN = "FALSE";
defparam PLL_inst.CLKOUT2_EN = "FALSE";
defparam PLL_inst.CLKOUT3_EN = "FALSE";
defparam PLL_inst.CLKOUT4_EN = "FALSE";
defparam PLL_inst.CLKOUT5_EN = "FALSE";
defparam PLL_inst.CLKOUT6_EN = "FALSE";
defparam PLL_inst.CLKFB_SEL = "INTERNAL";
defparam PLL_inst.CLKOUT0_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT1_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT2_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT3_DT_DIR = 1'b1;
defparam PLL_inst.CLKOUT0_DT_STEP = 0;
defparam PLL_inst.CLKOUT1_DT_STEP = 0;
defparam PLL_inst.CLKOUT2_DT_STEP = 0;
defparam PLL_inst.CLKOUT3_DT_STEP = 0;
defparam PLL_inst.CLK0_IN_SEL = 1'b0;
defparam PLL_inst.CLK0_OUT_SEL = 1'b0;
defparam PLL_inst.CLK1_IN_SEL = 1'b0;
defparam PLL_inst.CLK1_OUT_SEL = 1'b0;
defparam PLL_inst.CLK2_IN_SEL = 1'b0;
defparam PLL_inst.CLK2_OUT_SEL = 1'b0;
defparam PLL_inst.CLK3_IN_SEL = 1'b0;
defparam PLL_inst.CLK3_OUT_SEL = 1'b0;
defparam PLL_inst.CLK4_IN_SEL = 2'b00;
defparam PLL_inst.CLK4_OUT_SEL = 1'b0;
defparam PLL_inst.CLK5_IN_SEL = 1'b0;
defparam PLL_inst.CLK5_OUT_SEL = 1'b0;
defparam PLL_inst.CLK6_IN_SEL = 1'b0;
defparam PLL_inst.CLK6_OUT_SEL = 1'b0;
defparam PLL_inst.DYN_DPA_EN = "FALSE";
defparam PLL_inst.CLKOUT0_PE_COARSE = 0;
defparam PLL_inst.CLKOUT0_PE_FINE = 0;
defparam PLL_inst.CLKOUT1_PE_COARSE = 0;
defparam PLL_inst.CLKOUT1_PE_FINE = 0;
defparam PLL_inst.CLKOUT2_PE_COARSE = 0;
defparam PLL_inst.CLKOUT2_PE_FINE = 0;
defparam PLL_inst.CLKOUT3_PE_COARSE = 0;
defparam PLL_inst.CLKOUT3_PE_FINE = 0;
defparam PLL_inst.CLKOUT4_PE_COARSE = 0;
defparam PLL_inst.CLKOUT4_PE_FINE = 0;
defparam PLL_inst.CLKOUT5_PE_COARSE = 0;
defparam PLL_inst.CLKOUT5_PE_FINE = 0;
defparam PLL_inst.CLKOUT6_PE_COARSE = 0;
defparam PLL_inst.CLKOUT6_PE_FINE = 0;
defparam PLL_inst.DYN_PE0_SEL = "FALSE";
defparam PLL_inst.DYN_PE1_SEL = "FALSE";
defparam PLL_inst.DYN_PE2_SEL = "FALSE";
defparam PLL_inst.DYN_PE3_SEL = "FALSE";
defparam PLL_inst.DYN_PE4_SEL = "FALSE";
defparam PLL_inst.DYN_PE5_SEL = "FALSE";
defparam PLL_inst.DYN_PE6_SEL = "FALSE";
defparam PLL_inst.DE0_EN = "FALSE";
defparam PLL_inst.DE1_EN = "FALSE";
defparam PLL_inst.DE2_EN = "FALSE";
defparam PLL_inst.DE3_EN = "FALSE";
defparam PLL_inst.DE4_EN = "FALSE";
defparam PLL_inst.DE5_EN = "FALSE";
defparam PLL_inst.DE6_EN = "FALSE";
defparam PLL_inst.RESET_I_EN = "FALSE";
defparam PLL_inst.RESET_O_EN = "FALSE";
defparam PLL_inst.ICP_SEL = 6'bXXXXXX;
defparam PLL_inst.LPF_RES = 3'bXXX;
defparam PLL_inst.LPF_CAP = 2'b00;
defparam PLL_inst.SSC_EN = "FALSE";
defparam PLL_inst.DYN_IDIV_SEL = "FALSE";
defparam PLL_inst.DYN_FBDIV_SEL = "FALSE";
defparam PLL_inst.DYN_MDIV_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV0_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV1_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV2_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV3_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV4_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV5_SEL = "FALSE";
defparam PLL_inst.DYN_ODIV6_SEL = "FALSE";
defparam PLL_inst.DYN_DT0_SEL = "FALSE";
defparam PLL_inst.DYN_DT1_SEL = "FALSE";
defparam PLL_inst.DYN_DT2_SEL = "FALSE";
defparam PLL_inst.DYN_DT3_SEL = "FALSE";
defparam PLL_inst.DYN_ICP_SEL = "TRUE";
defparam PLL_inst.DYN_LPF_SEL = "TRUE";
endmodule //Gowin_PLL_MOD
`timescale 1ns/1ns
module PLL_INIT
#(
parameter CLK_PERIOD = 50,
parameter MULTI_FAC = 30
)
(
input CLKIN,
input I_RST,
input PLLLOCK,
output O_RST,
output [5:0] ICPSEL,
output [2:0] LPFRES,
output O_LOCK
);
localparam WAIT_TIME = 'd2000_000;
localparam WAIT_CNT = (WAIT_TIME + CLK_PERIOD - 1) / CLK_PERIOD;
localparam WAIT_WIDTH = $clog2(WAIT_CNT + 1);
reg [WAIT_WIDTH-1:0] waitcnt = 'd0;
reg [3:0] RomAddr = 'd0;
reg [15:0] Rom [15:0];
reg [15:0] RomDreg ='d0;
wire [5:0] Regicp = RomDreg[5:0];
wire [2:0] Regres = RomDreg[10:8];
reg Waitlock = 'd0;
reg [7:0] locksig = 8'b0000_0000;
reg laststep = 1'b0;
wire validsig = RomDreg[12];
reg [1:0]enable_r = 2'b00;
wire Enable = enable_r[1];
always @(posedge CLKIN or posedge I_RST)
begin
if (I_RST)
enable_r <= 2'b00;
else
begin
enable_r <= {enable_r[0], 1'b1};
end
end
always @(posedge CLKIN or negedge Enable)
begin
if (Enable == 1'b0)
begin
RomDreg <= 16'h0000;
Rom[00] <= 16'h1400; //1
Rom[01] <= (MULTI_FAC > 34) ? 16'h1401
: (MULTI_FAC > 16) ? 16'h1400
: 16'h1400; //2
Rom[02] <= (MULTI_FAC > 34) ? 16'h1501
: (MULTI_FAC > 16) ? 16'h1500
: 16'h1500; //3
Rom[03] <= (MULTI_FAC > 34) ? 16'h1503
: (MULTI_FAC > 16) ? 16'h1501
: 16'h1500; //4
Rom[04] <= (MULTI_FAC > 34) ? 16'h1507
: (MULTI_FAC > 16) ? 16'h1503
: 16'h1501; //5
Rom[05] <= (MULTI_FAC > 34) ? 16'h0605
: (MULTI_FAC > 16) ? 16'h0602
: 16'h0601; //6
Rom[06] <= 16'h0000; //over
Rom[07] <= (MULTI_FAC > 34) ? 16'h1402
: (MULTI_FAC > 16) ? 16'h1401
: 16'h1400; //2.5
Rom[08] <= (MULTI_FAC > 34) ? 16'h1502
: (MULTI_FAC > 16) ? 16'h1501
: 16'h1500; //3.5
Rom[09] <= (MULTI_FAC > 34) ? 16'h1504
: (MULTI_FAC > 16) ? 16'h1502
: 16'h1501; //4.5
Rom[10] <= (MULTI_FAC > 34) ? 16'h1603
: (MULTI_FAC > 16) ? 16'h1601
: 16'h1600; //5.5
Rom[11] <= 16'h1400; //1.5
Rom[12] <= 16'h0000;
Rom[13] <= 16'h0000;
Rom[14] <= 16'h0000;
Rom[15] <= 16'h0000;
end
else
RomDreg <= Rom[RomAddr[3:0]];
end
reg [3:0]RomAddrVld = 'd0;
always @ (*) begin
casex (locksig[5:0])
6'b111_111 : RomAddrVld = 4'd8;
6'b011_111 : RomAddrVld = 4'd8;
6'b111_110 : RomAddrVld = 4'd8;
6'b111_10x : RomAddrVld = 4'd9;
6'bx01_111 : RomAddrVld = 4'd7;
6'b011_110 : RomAddrVld = 4'd8;
6'bxx0_111 : RomAddrVld = 4'd1;
6'bx01_110 : RomAddrVld = 4'd2;
6'b011_10x : RomAddrVld = 4'd3;
6'b111_0xx : RomAddrVld = 4'd4;
6'bxxx_011 : RomAddrVld = 4'd1;
6'bxx0_110 : RomAddrVld = 4'd7;
6'bx01_100 : RomAddrVld = 4'd8;
6'b011_000 : RomAddrVld = 4'd9;
6'b110_000 : RomAddrVld = 4'd10;
6'bxxx_x01 : RomAddrVld = 4'd0;
6'bxxx_010 : RomAddrVld = 4'd1;
6'bxx0_100 : RomAddrVld = 4'd2;
6'bx01_000 : RomAddrVld = 4'd3;
6'b010_000 : RomAddrVld = 4'd4;
6'b100_000 : RomAddrVld = 4'd5;
6'b000_000 : RomAddrVld = 4'd8;
default : RomAddrVld = 4'd8;
endcase
end
reg [3:0]state='d0;
localparam IDLE = 4'd0;
localparam STATE1 = 4'd1;
localparam STATE2 = 4'd2;
localparam STATE3 = 4'd3;
localparam STATE4 = 4'd4;
localparam STATE5 = 4'd5;
localparam STATE6 = 4'd6;
localparam STATE7 = 4'd7;
always @(posedge CLKIN or negedge Enable)
begin
if (Enable == 1'b0)
begin
state <= IDLE;
RomAddr<=4'b0000;
laststep <= 1'b0;
end
else
begin
case (state)
IDLE:
begin
state<=STATE1;
end
STATE1:
begin
state<=STATE2;
end
STATE2:
begin
if (laststep==1'b1)
state<=STATE7;
else
state<=STATE3;
end
STATE3:
begin
if (Waitlock==1'b1)
state<=STATE4;
else
state<= STATE3;
end
STATE4:
begin
state<=STATE5;
end
STATE5:
begin
if (validsig==1'b1)
begin
RomAddr <= RomAddr + 1;
state <= STATE1;
end
else if (validsig==1'b0 && laststep==1'b0)
state <= STATE6;
end
STATE6:
begin
RomAddr <= RomAddrVld;
laststep <= 1'b1;
state <= STATE1;
end
STATE7:
begin
state<=STATE7;
end
default: state<=IDLE;
endcase
end
end
always @(posedge CLKIN)
begin
Waitlock <= (&waitcnt == 1'b1) ? 1'b1 : 1'b0;
waitcnt <= (state==STATE3) ? (waitcnt+1) : 'd0;
if (~Enable) locksig <= 8'b0000_0000;
else if (state==STATE4) locksig[RomAddr[3:0]] <= PLLLOCK;
end
assign ICPSEL = Regicp;
assign LPFRES = Regres;
assign O_RST = (~Enable) || (state==STATE2) ? 1'b1 : 1'b0;
assign O_LOCK = (state==STATE7) ? PLLLOCK : 1'b0;
endmodule

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// Generated by CIRCT firtool-1.139.0
// VCS coverage exclude_file
module mem_1024x8(
input [9:0] R0_addr,
input R0_en,
R0_clk,
output [7:0] R0_data,
input [9:0] W0_addr,
input W0_en,
W0_clk,
input [7:0] W0_data
);
reg [7:0] Memory[0:1023];
reg _R0_en_d0;
reg [9:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
always @(posedge W0_clk) begin
if (W0_en)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 8'bx;
endmodule

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module mem_1024x8 (
R0_addr,
R0_en,
R0_clk,
R0_data,
W0_addr,
W0_en,
W0_clk,
W0_data
);
input [9:0] R0_addr;
input R0_en;
input R0_clk;
output wire [7:0] R0_data;
input [9:0] W0_addr;
input W0_en;
input W0_clk;
input [7:0] W0_data;
reg [7:0] Memory [0:1023];
reg _R0_en_d0;
reg [9:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end
always @(posedge W0_clk)
if (W0_en)
Memory[W0_addr] <= W0_data;
assign R0_data = (_R0_en_d0 ? Memory[_R0_addr_d0] : 8'bxxxxxxxx);
endmodule

0
RTL/pll.v
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394
RTL/spade.sv
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@ -1,394 +0,0 @@
`ifdef COCOTB_SIM
`define COCOTB_CODE(name) \
string __top_module; \
string __vcd_file; \
initial begin \
if ($value$plusargs("TOP_MODULE=%s", __top_module) && __top_module == `"name`" && $value$plusargs("VCD_FILENAME=%s", __vcd_file)) begin \
$dumpfile (__vcd_file); \
$dumpvars (0, \name ); \
end \
end
`else
`define COCOTB_CODE(name)
`endif
module \std::cdc::sync2[1531] (
input clk_i,
input input_i,
output output__
);
`COCOTB_CODE( std::cdc::sync2[1531] )
logic \clk ;
assign \clk = clk_i;
logic \input ;
assign \input = input_i;
(* src = "<compiler dir>/stdlib/cdc.spade:14,14" *)
reg \sync1 ;
(* src = "<compiler dir>/stdlib/cdc.spade:15,14" *)
reg \sync2 ;
always @(posedge \clk ) begin
\sync1 <= \input ;
end
always @(posedge \clk ) begin
\sync2 <= \sync1 ;
end
assign output__ = \sync2 ;
endmodule
module \std::cdc::sync2_bool (
input clk_i,
input input_i,
output output__
);
`COCOTB_CODE( std::cdc::sync2_bool )
logic \clk ;
assign \clk = clk_i;
logic \input ;
assign \input = input_i;
(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *)
logic _e_544;
(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *)
\std::cdc::sync2[1531] \sync2_0 (.clk_i(\clk ), .input_i(\input ), .output__(_e_544));
assign output__ = _e_544;
endmodule
module \std::conv::tri_to_bool (
input t_i,
output output__
);
`COCOTB_CODE( std::conv::tri_to_bool )
logic \t ;
assign \t = t_i;
(* src = "<compiler dir>/stdlib/conv.spade:80,5" *)
logic _e_828;
(* src = "<compiler dir>/stdlib/conv.spade:80,5" *)
\std::conv::impl#12::as_bool \as_bool_0 (.self_i(\t ), .output__(_e_828));
assign output__ = _e_828;
endmodule
module \std::io::rising_edge (
input clk_i,
input value_i,
output output__
);
`COCOTB_CODE( std::io::rising_edge )
logic \clk ;
assign \clk = clk_i;
logic \value ;
assign \value = value_i;
(* src = "<compiler dir>/stdlib/io.spade:12,14" *)
reg \old_value ;
(* src = "<compiler dir>/core/ops.spade:255,29" *)
logic _e_2202;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2201;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_1034;
(* src = "<compiler dir>/core/ops.spade:297,29" *)
logic _e_2210;
(* src = "<compiler dir>/core/ops.spade:297,37" *)
logic _e_2211;
(* src = "<compiler dir>/core/ops.spade:297,9" *)
logic _e_2209;
(* src = "<compiler dir>/core/ops.spade:297,9" *)
logic _e_1032;
always @(posedge \clk ) begin
\old_value <= \value ;
end
assign _e_2202 = {\old_value };
assign _e_2201 = ~_e_2202;
assign _e_1034 = _e_2201;
assign _e_2210 = {\value };
assign _e_2211 = {_e_1034};
assign _e_2209 = _e_2210 & _e_2211;
assign _e_1032 = _e_2209;
assign output__ = _e_1032;
endmodule
module \std::io::falling_edge (
input clk_i,
input value_i,
output output__
);
`COCOTB_CODE( std::io::falling_edge )
logic \clk ;
assign \clk = clk_i;
logic \value ;
assign \value = value_i;
(* src = "<compiler dir>/stdlib/io.spade:27,14" *)
reg \old_value ;
(* src = "<compiler dir>/core/ops.spade:255,29" *)
logic _e_2220;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2219;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2218;
(* src = "<compiler dir>/core/ops.spade:297,29" *)
logic _e_2228;
(* src = "<compiler dir>/core/ops.spade:297,37" *)
logic _e_2229;
(* src = "<compiler dir>/core/ops.spade:297,9" *)
logic _e_2227;
(* src = "<compiler dir>/core/ops.spade:297,9" *)
logic _e_2226;
always @(posedge \clk ) begin
\old_value <= \value ;
end
assign _e_2220 = {\value };
assign _e_2219 = ~_e_2220;
assign _e_2218 = _e_2219;
assign _e_2228 = {_e_2218};
assign _e_2229 = {\old_value };
assign _e_2227 = _e_2228 & _e_2229;
assign _e_2226 = _e_2227;
assign output__ = _e_2226;
endmodule
module main (
input clk,
output[3:0] leds,
output tmds_clk,
output[2:0] tmds
);
`COCOTB_CODE( main )
logic[3:0] \leds_mut ;
assign leds = \leds_mut ;
logic \tmds_clk_mut ;
assign tmds_clk = \tmds_clk_mut ;
logic[2:0] \tmds_mut ;
assign tmds = \tmds_mut ;
(* src = "src/main.spade:9,35" *)
logic _e_2156;
(* src = "src/main.spade:9,35" *)
logic _e_2157_mut;
(* src = "src/main.spade:9,35" *)
logic _e_1733;
(* src = "src/main.spade:9,35" *)
logic _e_1733_mut;
(* src = "src/main.spade:9,9" *)
logic \clk_pll ;
(* src = "src/main.spade:9,9" *)
logic \clk_pll_wire_mut ;
(* src = "src/main.spade:10,37" *)
logic _e_2158;
(* src = "src/main.spade:10,37" *)
logic _e_2159_mut;
(* src = "src/main.spade:10,37" *)
logic _e_1737;
(* src = "src/main.spade:10,37" *)
logic _e_1737_mut;
(* src = "src/main.spade:10,9" *)
logic \lock_pll ;
(* src = "src/main.spade:10,9" *)
logic \lock_pll_wire_mut ;
localparam[31:0] _e_1748 = 32'd50000000;
(* src = "<compiler dir>/core/ops.spade:53,9" *)
logic _e_1746;
localparam[31:0] _e_1750 = 32'd0;
localparam[31:0] _e_1754 = 32'd1;
(* src = "src/main.spade:13,75" *)
logic[31:0] _e_1752;
(* src = "src/main.spade:13,38" *)
logic[31:0] _e_1745;
(* src = "src/main.spade:13,18" *)
reg[31:0] \counter ;
localparam[31:0] _e_1760 = 32'd0;
(* src = "<compiler dir>/core/ops.spade:53,9" *)
logic _e_1758;
(* src = "<compiler dir>/core/ops.spade:255,29" *)
logic _e_2242;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2241;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_1762;
(* src = "src/main.spade:14,29" *)
logic _e_1757;
(* src = "src/main.spade:14,18" *)
reg \on ;
localparam[0:0] _e_1770 = 0;
localparam[0:0] _e_1771 = 0;
localparam[0:0] _e_1772 = 0;
(* src = "src/main.spade:19,16" *)
logic[2:0] _e_1769;
(* src = "<compiler dir>/core/ops.spade:255,29" *)
logic _e_2250;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2249;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2248;
(* src = "<compiler dir>/core/ops.spade:255,29" *)
logic _e_2258;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2257;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_1777;
(* src = "<compiler dir>/core/ops.spade:255,29" *)
logic _e_2266;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2265;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2264;
(* src = "<compiler dir>/core/ops.spade:255,29" *)
logic _e_2274;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_2273;
(* src = "<compiler dir>/core/ops.spade:255,9" *)
logic _e_1781;
(* src = "src/main.spade:21,16" *)
logic[3:0] _e_1774;
assign _e_2156 = _e_2157_mut;
assign _e_1733 = {_e_2156};
assign {_e_2157_mut} = _e_1733_mut;
assign \clk_pll = _e_1733;
assign _e_1733_mut = \clk_pll_wire_mut ;
assign _e_2158 = _e_2159_mut;
assign _e_1737 = {_e_2158};
assign {_e_2159_mut} = _e_1737_mut;
assign \lock_pll = _e_1737;
assign _e_1737_mut = \lock_pll_wire_mut ;
(* src = "src/main.spade:11,5" *)
pll \pll_0 (.clkin(\clk ), .init_clk(\clk ), .clkout0(\clk_pll_wire_mut ), .lock(\lock_pll_wire_mut ));
assign _e_1746 = \counter == _e_1748;
(* src = "src/main.spade:13,75" *)
\core::ops::impl#77::wrapping_add[1533] \wrapping_add_0 (.self_i(\counter ), .rhs_i(_e_1754), .output__(_e_1752));
assign _e_1745 = _e_1746 ? _e_1750 : _e_1752;
always @(posedge \clk_pll ) begin
\counter <= _e_1745;
end
assign _e_1758 = \counter == _e_1760;
assign _e_2242 = {\on };
assign _e_2241 = ~_e_2242;
assign _e_1762 = _e_2241;
assign _e_1757 = _e_1758 ? _e_1762 : \on ;
always @(posedge \clk_pll ) begin
\on <= _e_1757;
end
assign \tmds_clk_mut = \clk_pll ;
assign _e_1769 = {_e_1772, _e_1771, _e_1770};
assign \tmds_mut = _e_1769;
assign _e_2250 = {\on };
assign _e_2249 = ~_e_2250;
assign _e_2248 = _e_2249;
assign _e_2258 = {\on };
assign _e_2257 = ~_e_2258;
assign _e_1777 = _e_2257;
assign _e_2266 = {\on };
assign _e_2265 = ~_e_2266;
assign _e_2264 = _e_2265;
assign _e_2274 = {\lock_pll };
assign _e_2273 = ~_e_2274;
assign _e_1781 = _e_2273;
assign _e_1774 = {_e_1781, _e_2264, _e_1777, _e_2248};
assign \leds_mut = _e_1774;
endmodule
module \std::conv::impl#10::as_clock (
input self_i,
output output__
);
`COCOTB_CODE( std::conv::impl#10::as_clock )
logic \self ;
assign \self = self_i;
logic _e_872;
assign _e_872 = \self ;
assign output__ = _e_872;
endmodule
module \std::conv::impl#10::as_uint (
input self_i,
output output__
);
`COCOTB_CODE( std::conv::impl#10::as_uint )
logic \self ;
assign \self = self_i;
logic _e_876;
assign _e_876 = \self ;
assign output__ = _e_876;
endmodule
module \std::conv::impl#11::as_bool (
input self_i,
output output__
);
`COCOTB_CODE( std::conv::impl#11::as_bool )
logic \self ;
assign \self = self_i;
logic _e_887;
assign _e_887 = \self ;
assign output__ = _e_887;
endmodule
module \std::conv::impl#12::as_bool (
input self_i,
output output__
);
`COCOTB_CODE( std::conv::impl#12::as_bool )
logic \self ;
assign \self = self_i;
logic _e_895;
assign _e_895 = \self ;
assign output__ = _e_895;
endmodule
module \std::default::impl#17::hacky_default (
input self_i,
output output__
);
`COCOTB_CODE( std::default::impl#17::hacky_default )
logic \self ;
assign \self = self_i;
localparam[0:0] _e_971 = 0;
assign output__ = _e_971;
endmodule
module \std::default::impl#18::hacky_default (
);
`COCOTB_CODE( std::default::impl#18::hacky_default )
endmodule
module \core::ops::impl#77::wrapping_add[1533] (
input[31:0] self_i,
input[31:0] rhs_i,
output[31:0] output__
);
`COCOTB_CODE( core::ops::impl#77::wrapping_add[1533] )
logic[31:0] \self ;
assign \self = self_i;
logic[31:0] \rhs ;
assign \rhs = rhs_i;
(* src = "<compiler dir>/core/ops.spade:166,62" *)
logic[32:0] _e_1923;
logic[32:0] \bits ;
(* src = "<compiler dir>/core/ops.spade:167,34" *)
logic[31:0] _e_1928;
logic[31:0] _e_1927;
assign _e_1923 = \self + \rhs ;
assign \bits = _e_1923;
assign _e_1928 = \bits [31-:32];
assign _e_1927 = _e_1928;
assign output__ = _e_1927;
endmodule
`default_nettype none

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@ -1,306 +0,0 @@
module \std::cdc::sync2[1531] (
clk_i,
input_i,
output__
);
input clk_i;
input input_i;
output wire output__;
wire \clk ;
assign \clk = clk_i;
wire \input ;
assign \input = input_i;
(* src = "<compiler dir>/stdlib/cdc.spade:14,14" *) reg \sync1 ;
(* src = "<compiler dir>/stdlib/cdc.spade:15,14" *) reg \sync2 ;
always @(posedge \clk ) \sync1 <= \input ;
always @(posedge \clk ) \sync2 <= \sync1 ;
assign output__ = \sync2 ;
endmodule
module \std::cdc::sync2_bool (
clk_i,
input_i,
output__
);
input clk_i;
input input_i;
output wire output__;
wire \clk ;
assign \clk = clk_i;
wire \input ;
assign \input = input_i;
(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *) wire _e_544;
(* src = "<compiler dir>/stdlib/cdc.spade:31,14" *) \std::cdc::sync2[1531] \sync2_0 (
.clk_i(\clk ),
.input_i(\input ),
.output__(_e_544)
);
assign output__ = _e_544;
endmodule
module \std::conv::tri_to_bool (
t_i,
output__
);
input t_i;
output wire output__;
wire \t ;
assign \t = t_i;
(* src = "<compiler dir>/stdlib/conv.spade:80,5" *) wire _e_828;
(* src = "<compiler dir>/stdlib/conv.spade:80,5" *) \std::conv::impl#12::as_bool \as_bool_0 (
.self_i(\t ),
.output__(_e_828)
);
assign output__ = _e_828;
endmodule
module \std::io::rising_edge (
clk_i,
value_i,
output__
);
input clk_i;
input value_i;
output wire output__;
wire \clk ;
assign \clk = clk_i;
wire \value ;
assign \value = value_i;
(* src = "<compiler dir>/stdlib/io.spade:12,14" *) reg \old_value ;
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2202;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2201;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1034;
(* src = "<compiler dir>/core/ops.spade:297,29" *) wire _e_2210;
(* src = "<compiler dir>/core/ops.spade:297,37" *) wire _e_2211;
(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2209;
(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_1032;
always @(posedge \clk ) \old_value <= \value ;
assign _e_2202 = {\old_value };
assign _e_2201 = ~_e_2202;
assign _e_1034 = _e_2201;
assign _e_2210 = {\value };
assign _e_2211 = {_e_1034};
assign _e_2209 = _e_2210 & _e_2211;
assign _e_1032 = _e_2209;
assign output__ = _e_1032;
endmodule
module \std::io::falling_edge (
clk_i,
value_i,
output__
);
input clk_i;
input value_i;
output wire output__;
wire \clk ;
assign \clk = clk_i;
wire \value ;
assign \value = value_i;
(* src = "<compiler dir>/stdlib/io.spade:27,14" *) reg \old_value ;
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2220;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2219;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2218;
(* src = "<compiler dir>/core/ops.spade:297,29" *) wire _e_2228;
(* src = "<compiler dir>/core/ops.spade:297,37" *) wire _e_2229;
(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2227;
(* src = "<compiler dir>/core/ops.spade:297,9" *) wire _e_2226;
always @(posedge \clk ) \old_value <= \value ;
assign _e_2220 = {\value };
assign _e_2219 = ~_e_2220;
assign _e_2218 = _e_2219;
assign _e_2228 = {_e_2218};
assign _e_2229 = {\old_value };
assign _e_2227 = _e_2228 & _e_2229;
assign _e_2226 = _e_2227;
assign output__ = _e_2226;
endmodule
module main (
clk,
leds,
tmds_clk,
tmds
);
input clk;
output wire [3:0] leds;
output wire tmds_clk;
output wire [2:0] tmds;
wire [3:0] \leds_mut ;
assign leds = \leds_mut ;
wire \tmds_clk_mut ;
assign tmds_clk = \tmds_clk_mut ;
wire [2:0] \tmds_mut ;
assign tmds = \tmds_mut ;
(* src = "src/main.spade:9,35" *) wire _e_2156;
(* src = "src/main.spade:9,35" *) wire _e_2157_mut;
(* src = "src/main.spade:9,35" *) wire _e_1733;
(* src = "src/main.spade:9,35" *) wire _e_1733_mut;
(* src = "src/main.spade:9,9" *) wire \clk_pll ;
(* src = "src/main.spade:9,9" *) wire \clk_pll_wire_mut ;
(* src = "src/main.spade:10,37" *) wire _e_2158;
(* src = "src/main.spade:10,37" *) wire _e_2159_mut;
(* src = "src/main.spade:10,37" *) wire _e_1737;
(* src = "src/main.spade:10,37" *) wire _e_1737_mut;
(* src = "src/main.spade:10,9" *) wire \lock_pll ;
(* src = "src/main.spade:10,9" *) wire \lock_pll_wire_mut ;
localparam [31:0] _e_1748 = 32'd50000000;
(* src = "<compiler dir>/core/ops.spade:53,9" *) wire _e_1746;
localparam [31:0] _e_1750 = 32'd0;
localparam [31:0] _e_1754 = 32'd1;
(* src = "src/main.spade:13,75" *) wire [31:0] _e_1752;
(* src = "src/main.spade:13,38" *) wire [31:0] _e_1745;
(* src = "src/main.spade:13,18" *) reg [31:0] \counter ;
localparam [31:0] _e_1760 = 32'd0;
(* src = "<compiler dir>/core/ops.spade:53,9" *) wire _e_1758;
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2242;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2241;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1762;
(* src = "src/main.spade:14,29" *) wire _e_1757;
(* src = "src/main.spade:14,18" *) reg \on ;
localparam [0:0] _e_1770 = 0;
localparam [0:0] _e_1771 = 0;
localparam [0:0] _e_1772 = 0;
(* src = "src/main.spade:19,16" *) wire [2:0] _e_1769;
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2250;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2249;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2248;
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2258;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2257;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1777;
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2266;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2265;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2264;
(* src = "<compiler dir>/core/ops.spade:255,29" *) wire _e_2274;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_2273;
(* src = "<compiler dir>/core/ops.spade:255,9" *) wire _e_1781;
(* src = "src/main.spade:21,16" *) wire [3:0] _e_1774;
assign _e_2156 = _e_2157_mut;
assign _e_1733 = {_e_2156};
assign {_e_2157_mut} = _e_1733_mut;
assign \clk_pll = _e_1733;
assign _e_1733_mut = \clk_pll_wire_mut ;
assign _e_2158 = _e_2159_mut;
assign _e_1737 = {_e_2158};
assign {_e_2159_mut} = _e_1737_mut;
assign \lock_pll = _e_1737;
assign _e_1737_mut = \lock_pll_wire_mut ;
wire \clk ;
(* src = "src/main.spade:11,5" *) pll \pll_0 (
.clkin(\clk ),
.init_clk(\clk ),
.clkout0(\clk_pll_wire_mut ),
.lock(\lock_pll_wire_mut )
);
assign _e_1746 = \counter == _e_1748;
(* src = "src/main.spade:13,75" *) \core::ops::impl#77::wrapping_add[1533] \wrapping_add_0 (
.self_i(\counter ),
.rhs_i(_e_1754),
.output__(_e_1752)
);
assign _e_1745 = (_e_1746 ? _e_1750 : _e_1752);
always @(posedge \clk_pll ) \counter <= _e_1745;
assign _e_1758 = \counter == _e_1760;
assign _e_2242 = {\on };
assign _e_2241 = ~_e_2242;
assign _e_1762 = _e_2241;
assign _e_1757 = (_e_1758 ? _e_1762 : \on );
always @(posedge \clk_pll ) \on <= _e_1757;
assign \tmds_clk_mut = \clk_pll ;
assign _e_1769 = {_e_1772, _e_1771, _e_1770};
assign \tmds_mut = _e_1769;
assign _e_2250 = {\on };
assign _e_2249 = ~_e_2250;
assign _e_2248 = _e_2249;
assign _e_2258 = {\on };
assign _e_2257 = ~_e_2258;
assign _e_1777 = _e_2257;
assign _e_2266 = {\on };
assign _e_2265 = ~_e_2266;
assign _e_2264 = _e_2265;
assign _e_2274 = {\lock_pll };
assign _e_2273 = ~_e_2274;
assign _e_1781 = _e_2273;
assign _e_1774 = {_e_1781, _e_2264, _e_1777, _e_2248};
assign \leds_mut = _e_1774;
endmodule
module \std::conv::impl#10::as_clock (
self_i,
output__
);
input self_i;
output wire output__;
wire \self ;
assign \self = self_i;
wire _e_872;
assign _e_872 = \self ;
assign output__ = _e_872;
endmodule
module \std::conv::impl#10::as_uint (
self_i,
output__
);
input self_i;
output wire output__;
wire \self ;
assign \self = self_i;
wire _e_876;
assign _e_876 = \self ;
assign output__ = _e_876;
endmodule
module \std::conv::impl#11::as_bool (
self_i,
output__
);
input self_i;
output wire output__;
wire \self ;
assign \self = self_i;
wire _e_887;
assign _e_887 = \self ;
assign output__ = _e_887;
endmodule
module \std::conv::impl#12::as_bool (
self_i,
output__
);
input self_i;
output wire output__;
wire \self ;
assign \self = self_i;
wire _e_895;
assign _e_895 = \self ;
assign output__ = _e_895;
endmodule
module \std::default::impl#17::hacky_default (
self_i,
output__
);
input self_i;
output wire output__;
wire \self ;
assign \self = self_i;
localparam [0:0] _e_971 = 0;
assign output__ = _e_971;
endmodule
module \std::default::impl#18::hacky_default ;
endmodule
module \core::ops::impl#77::wrapping_add[1533] (
self_i,
rhs_i,
output__
);
input [31:0] self_i;
input [31:0] rhs_i;
output wire [31:0] output__;
wire [31:0] \self ;
assign \self = self_i;
wire [31:0] \rhs ;
assign \rhs = rhs_i;
(* src = "<compiler dir>/core/ops.spade:166,62" *) wire [32:0] _e_1923;
wire [32:0] \bits ;
(* src = "<compiler dir>/core/ops.spade:167,34" *) wire [31:0] _e_1928;
wire [31:0] _e_1927;
assign _e_1923 = \self + \rhs ;
assign \bits = _e_1923;
assign _e_1928 = \bits [31-:32];
assign _e_1927 = _e_1928;
assign output__ = _e_1927;
endmodule
`default_nettype none